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RISC-V RV32I RTL Verification using UVM

4.7
(8 ratings)
Course Instructor Sivakumar P R
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Course Overview

Course Curriculum

1 Subject

RISC-V RV32I RTL Verification using UVM

15 Exercises 67 Learning Materials

RISC-V Instruction Set Architecture

Why RISC-V Processor?

Video
6:50

RISC-V processor overview

Video
10:24

RISC-V ISA Overview

Video
12:13

RV32I R Type Instruction

Video
9:29

RV32I I Type Instruction

Video
7:47

RV32I S and B Type Instructions

Video
11:55

RV32I J and U Type Instructions

Video
12:35

RV32I Assembly Programs and Summary

Video
19:22

Knowledge Check - RISC-V Instruction Set Architecture

Exercise

RISC-V RV32I Processor

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

Knowledge Check : RISC-V RTL Architecture Design

Exercise

RISC-V RV32I 5 Stage Pipeline Processor

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

Knowledge Check : RISC-V RV32I 5 Stage Pipelined RTL Design

Exercise

Linux Operating System

Introduction to Linux Operating System

Video
1:15:00

vi Text Editor

Video
31:00

Universal Verification Methodology Overview

Introduction to UVM

Video
10:47

UVM Concepts

Video
4:37

UVM SoC TB

Video
8:49

UVM AHB UVC

Video
7:8

UVM SoC TB Examples

Video
5:31

Knowledge Check : Introduction to UVM

Exercise

UVM Reference Guide

UVM - Quick Reference Guide

PDF

UVM TB Architecture and Base Class Hierarchy

UVM Testbench Architecture

Video
13:48

UVM Base Class Hierarchy

Video
14:31

Knowledge Check - UVM TB Architecture and Base Class Hierarchy

Exercise

UVM Factory

UVM Factory - Importance of using factory

Video
11:19

UVM Factory - Registration Process

Video
6:2

UVM Factory - Create Method and Factory Overriding

Video
11:47

Knowledge Check - UVM Factory

Exercise

UVM - Stimulus Modelling & Testbench Overview

UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Video
10:22

UVM Stimulus Modelling - Overriding the predefined do_ methods

Video
10:41

UVM - TB Overview

Video
10:44

Knowledge Check - UVM Stimulus Modelling & TB Overview

Exercise

UVM Phases & Reporting Mechanism

UVM Phases - Necessity of Phases & pre-run Phases

Video
16:27

UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Video
13:13

UVM Reporting Mechanism

Video
15:1

Knowledge Check - UVM Phases & Reporting Mechanism

Exercise

UVM TLM Ports and Configuration

UVM TLM Ports - Blocking put and get ports

Video
11:35

UVM TLM Ports - TLM FIFO and Analysis Ports

Video
13:1

UVM Configuration - Introduction to Configuration Facility

Video
13:2

UVM Configuration - Configuration class and Configuration of Virtual Interface

Video
9:31

Knowledge Check - UVM TLM Ports and Configuration

Exercise

UVM - Creating UVM Testbench Components

Creating UVM TB Components - Sequencers & Drivers

Video
15:1

Creating UVM TB Components - Monitor, Agents, Env and Testcases

Video
16:30

Knowledge Check - UVM - Creating UVM Testbench Components

Exercise

UVM Sequences

UVM Sequences - Introduction and Sequence item flow

Video
11:35

UVM Sequences - Starting the sequences and Default Sequence

Video
15:17

Knowledge Check - UVM Sequences

Exercise

UVM - Virtual Sequences & Virtual Sequencers

UVM Virtual Sequences & Virtual Sequencers - Introduction

Video
13:33

UVM Virtual Sequences & Virtual Sequencers - implementation

Video
8:22

Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

Exercise

UVM Callbacks & Events

UVM Callbacks

Video
9:23

UVM Events

Video
9:6

Knowledge Check - UVM Callbacks & Events

Exercise

UVM - Creating Scoreboard

UVM Creating Scoreboard

Video
9:20

Knowledge Check - UVM - Creating Scoreboard

Exercise

UVM - Register Abstraction Layer

UVM RAL - Intro & Definition of Register Block

Video
15:55

UVM RAL - Adapter, Predictor and Integration

Video
20:36

UVM RAL - Definition of Register Sequences

Video
11:55

Knowledge Check - UVM RAL

Exercise

UVM Lab Setup guide - reference manuals

UVM Labs User Guide

PDF

VPN Configuration Guide

PDF

UVM Labs

UVM Lab Manual

PDF

Lab1 Solution : Stimulus Modeling

Video
16:2

Lab2 Solution : Factory Overriding

Video
8:19

Lab3 Solution : UVM Phases

Video
10:22

Lab4 Solution : Creating UVM agent

Video
11:44

Lab5 Solution : UVM Sequences

Video
13:22

Lab6 Solution : Virtual Interface

Video
5:50

Lab7 Solution : Agent Integration

Video
8:12

Lab8 Solution : UVM Socreboard

Video
6:39

Lab9 Solution : SoC - UVM VE implementation

Video
8:41

Lab10 Solution : Coverage & Regression

Video
4:33

Course Instructor

tutor image

Sivakumar P R

17 Courses   •   1935 Students

CEO and Founder, Maven Silicon

Ratings & Reviews

4.7 /5

9 ratings

8 reviews

5

67%

4

33%

3

0%

2

0%

1

0%
S
Susmitha

5 months ago

AK
Anupam Kumari

a year ago

Very good course for UVM
SM
Shashank Mistry

2 years ago

good

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