RISC-V RV32I RTL Design
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Course Overview
Course Curriculum
1 Subject
RISC-V RV32I RTL Design
2 Exercises • 12 Learning Materials
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Course Instructor
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Sivakumar P R
17 Courses • 1948 Students
CEO and Founder, Maven Silicon
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