VLSI SoC Design Course

Advanced VLSI Verification

  • 4.7 | 37 Ratings
  • 191 Students enrolled
  • Certified course

About Course

  Language English

Advanced VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail. Finally, it also walks you through UVM methodology concepts and explains the need of using IEEE standard methodologies like UVM to create SystemVerilog based testbenches.


  • Verification Methodology Overview
  • SystemVerilog for Verification
  • SystemVerilog HVL - Hands-on
  • Universal Verification Methodology
  • UVM - Hands-on

Verification Methodology Overview Module: It starts with a good overview and explains the need of verification. Then it explains the functional verification process, testbench architecture and constraint random coverage driven verification methodology in detail. Finally, it walks you through all the verification methodologies like linting, code coverage, functional coverage, verification planning & management and Assertion Based verification and give you a good exposure how we verify RTL design thoroughly.

Systemverilog Module: It trains you extensively on creating the testbenches using OOP, constraint random simulation and verification sign-off using functional coverage. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, etc. in detail and trains you extensively on creating the class-based verification environment.

SystemVerilog HVL Hands-on Module: It provides all the lab exercises and case study examples to understand all the SystemVerilog language concepts, syntax and semantics of all the language features very well. With this lab practice and coding expertise, one can understand how a SV class based verification environment can be created to verify the RTL design.  

UVM Module: It begins with a good overview of UVM methodology, explaining the concepts like agents and UVCs with various examples like AHB UVCs and SOC UVM testbenches. With this overview it walks you through all the concepts like UVM TB frame work, base class library, factory, sequences, phases, reporting mechanism, TLM ports, virtual sequences, events, call backs, UVCs, Scoreboard,  UVM environment, etc and guide you to do the lab exercises to understand all the concepts very well. This course explains the need and usage of UVM with various examples like IP and SOC level testbenches. 

UVM Hands-on Module: It provides all the lab exercises and examples to understand all the UVM concepts, syntax and semantics of all the language features very well. With the help of this hands-on course you can learn the nuts and bolts of UVM and grow as a UVM expert in the functional verification domain.

USP : This course is very different from the standard textbooks and training courses available in the market. This advanced verification course is completely based on a standard testbench architecture which can be used for creating SystemVerilog testbenches and at the same they can be easily migrated to UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.

Any electronics engineer with a good knowledge in RTL design using Verilog HDL can learn all the verification methodologies and SystemVerilog language concepts from this course and grow as a hand-on verification expert.

Prerequisite: Any electronics/electrical engineering graduate with a good knowledge in RTL design using Verilog HDL.

Read full details


  • 1: Verification Methodology Overview

  • Lecture 1 Introduction to Verification Methodology 22:24
  • Lecture 2 Verification Process 21:46
  • Lecture 3 Reusable TB 07:24
  • Lecture 4 Verification Environment Architecture 19:01
  • Lecture 5 Constraint Random Coverage Driven Verification 25:36
  • Lecture 6 Verification Methodologies & Summary 27:11
  • Quiz 1 Knowledge Check - Verification Methodology Overview 15 Questions
  • 2: Introduction to Linux OS, vi Editor & Simulation Tool

  • Lecture 7 Introduction to Linux Operating System 75:00
  • Lecture 8 'vi' Text Editor 30:59
  • Lecture 9 Linux Lab Manual 5 Pages
VIew Full Curriculum


37 Ratings
5 73% 4 24% 3 3% 2 0% 1 0%
  • Aashish Ughareja
    8 April 2021

    Don't have words to describe how useful this course is for Verification engineer. Excellent, shandaar, jabrdasttttt

  • Rachana Uday S
    7 April 2021

    Very useful!

    3 April 2021

    Very good

  • Swapnil Deshmukh
    3 April 2021


  • 29 March 2021

    I don’t t have a word how to say thank you but this course is shandar, jabrdast for verification.

    25 March 2021

    Well structured course. Helpful for job placements.

  • Kevin
    17 March 2021

    Well recorded video sessions

  • Kinjal
    6 March 2021

    excellent learning.

  • 1 March 2021

    Well explained videos

  • 27 February 2021

    excellent learning.

  • Johnu Ragavi
    23 February 2021

    Easy way of learning

  • 20 February 2021

    well explained

  • Chandan
    20 February 2021

    Easy learning journey

  • 19 February 2021

    Excellent learning.

    14 February 2021

    Really helpful, Labs are so helpful, I'll suggest my juniors take up the course. It will be helpful if we get placement assistance as well.

  • Ameya Milind Deshpande
    25 January 2021

    Very good

  • Bhanu Prakash Puvvada
    14 January 2021

    Content and pace of the course was good

  • Ashutosh Sahoo
    5 January 2021

    Nice Course

  • Johnatan Antonioli
    2 January 2021

    It was a very good way to get started with SystemVerilog and to have an overall understand of what UVM is, and how to use it for design verification.

  • 23 December 2020

    Covers every aspect required to write a tb step by step with clarity and in depth understanding. Good amount of labs to provide hand on. Very helpful for beginers.

  • Ila Segu
    23 December 2020

    Great course!

  • Siddartha Gajula
    20 December 2020

    Good course

  • Bhuvaneswari Putluru
    5 December 2020


  • Gaurav Sharma
    28 November 2020

    Content is great, great interactive QA sessions, ready to help anytime.

  • Bhanu Prakash Puvvada
    24 November 2020

    I am very much satisfied with the training and training faculty. The guidelines given by trainers were excellent. It is well-designed course with practical orientation. As it is a lab oriented program, it had given me better understanding with hands-on. If you want to optimize and sharpen your VLSI based Engineering skills, it’s my personal suggestion to join Maven silicon.

  • Shiban
    22 November 2020

    So far I have learned many new concepts that are not been taught elsewhere. Continuous support ecosystem you get here is remarkable. I would definitely recommend this course, specially for freshers who are willing to get a job as a Verification Engineer. Despite the fact it is an online course you will be helped as soon as you post your doubt and there is always someone to help you (mostly on the same day).

  • Juturu Raviteja Reddy
    22 September 2020

    I did an internship at INTEL during my second year of MTECH. Due to the COVID-19 situation, my conversion at INTEL got affected. I was so disappointed and frightened about my future. My confidence level was not high, so I wanted to acquire more technical skills by learning Verification so that I can attend Offcampus interviews. But I was unable to find the right material/websites to learn verification thoroughly. Then I heard that Maven Silicon is offering Verification courses online. I joined immediately and the videos of course were very detailed, tools were provided to us for practice. The teaching staff was always available to clarify my doubts and I was able to complete the entire course in less than 2 months. With that confidence, I attended an interview in one semiconductor company, cracked 3 rounds of interviews, and got a job offer. I also got a job offer from INTEL at the same time and I accepted it. I thank the Maven Silicon team for providing a great platform to learn design and verification aspects in VLSI and making many people like me gain the confidence to crack interviews in semiconductor companies. Once again, thank you so much Maven Silicon Team.

  • Er Surajit Bhattacherjee
    5 July 2020

    Amazing Analogy

  • Dheeraj Kumar
    4 June 2020

    The content of the course and training is really fabulous

  • Harishma P
    4 June 2020

    Good material and class. Knowledge shared is useful

  • Spurthi S
    4 June 2020

    Have good trainers and IT support. Live Q&A session helps a lot.

  • Show more reviews