RISC-V RV32I RTL Design
Master RISC-V RV32I RTL Design with Maven Silicon, gaining hands-on experience in developing RTL designs for the RV32I instruction set architecture.
/CourseBundles(29)/669-RISC-V_RV32I_RTL_Design-min.png)
Course Overview
Dive into the world of RISC-V RV32I RTL Design with key modules such as "RISC-V RV32I Reference Guide," "RISC-V RV32I RTL Architecture Design," and "RISC-V RV32I 5 Stage Pipelined RTL Design." Explore the intricacies of RTL design and gain hands-on experience in building a 5-stage pipelined architecture using RISC-V.
Course Curriculum
1 Subject
RISC-V RV32I RTL Design
2 Exercises • 12 Learning Materials
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Course Instructor
/101894-Maven_Logo_(elearn_profile_pic)_(2).png){kind=logo}
Sivakumar P R
17 Courses • 1963 Students
CEO and Founder, Maven Silicon
Ratings & Reviews
4.7 /5
133 ratings
●
127 reviews
5
4
3
2
1
By clicking on Continue, I accept the Terms & Conditions,
Privacy Policy & Refund Policy