Workshop Topic: VLSI Design using Verilog HDL

Date :  20/Jan/2019

Time :  9:00 AM to 01:00 PM

Speaker : Mr. P R Sivakumar , CEO Maven Silicon,

Venue :  Maven Silicon

Agenda :

Overview of VLSI Design

• IPs, Chips and SoCs
• SoC Design
• ASIC Vs FPGA

RTL Design using Verilog HDL

• Overview of Verilog
  • Verilog Language Concepts
  • Verilog Language Basics and Constructs
  • Verilog Abstraction Levels
• Data Types
  • Data type concepts 
  • Nets and Registers 
  • Non hardware equivalent variables 
  • Arrays 
• Verilog Operators 
  • Logical operators 
  • Bitwise and Reduction operators 
  • Concatenation and Conditional 
  • Relational and Arithmetic 
  • Shift and Equality operators 
  • Operators precedence
• Verilog RTL Coding Style - Summary
• Verilog Labs - Hands On Session

Q & A Session

Take away :

• Participation Certificate
• Scholarship Coupon 

CEO Message

“  I am very glad for this opportunity to interact with the student community and share my experience through this workshop. I have personally designed this workshop agenda, after long contemplation on the needs of fresh electronics engineering students. 

I am sure this workshop will help the attendee to understand the concepts of RTL design using Verilog HDL  and also gain the hand on experience. So, participate in this workshop, interact with me and learn from my experience. This workshop will help if you are very passionate about VLSI technology and want to work in the Chip Design Industry. 

Looking forward to meeting you all through this workshop. “

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