Advanced Design for Testability
Optimize your team's designs with custom training in Design for Testability (DFT) from Maven Silicon, developing strategies for building robust and testable VLSI circuits.
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Course Overview
Welcome to the Design for Testability (DFT) course, where you'll gain valuable insights into testing strategies and methodologies in the VLSI domain. This module covers Intro to Testing, Fault Collapsing, ATPG, Fault Simulation, DFT Basics, Scan Insertion & Test Compression, Boundary Scan & BIST, and various miscellaneous concepts. The Tessent Shell Overview and DFT Labs provide hands-on experiences to enhance your practical skills. The course includes a pre-assessment test to gauge your understanding before delving into the intricacies of DFT. Be prepared to explore advanced digital design concepts, Verilog HDL, and RISC-V ISA & RV32I RTL Design in subsequent modules for a holistic VLSI learning journey.
Schedule of Classes
Course Curriculum
5 Subjects
Advanced Digital Design
24 Exercises • 54 Learning Materials
Why Semiconductors?
Why Semiconductors?
Video
00:10:53
Semiconductor Supply Chain
Semiconductor Supply CHain
Video
00:12:32
Semiconductor Ecosystem
Semiconductor Ecosystem
Video
00:13:34
AI-driven Semiconductor Industry
AI-Driven
Video
00:07:22
Knowledge Check - Semiconductor Industry
Exercise
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:44
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:08
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:06
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
00:13:26
Number System and Codes
Number Systems and Codes - Basics
Video
00:37:45
Knowledge Check : Number systems-1
Exercise
Number Systems
Video
00:27:09
Codes
Video
00:10:09
Knowledge Check : Number system and Codes-2
Exercise
Logic Circuits
Logic Circuits
Video
00:55:07
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
00:50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Combinational Circuits - Basics
Combinational Circuits - I
Video
00:28:25
Knowledge check : Combinational Circuits Basics-1
Exercise
Combinational Circuits - II
Video
00:44:08
Knowledge Check : Combinational Circuits Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
00:21:08
Combinational Logic Circuits - Delays
Video
00:09:11
Encoders, decoders and Magnitude Comparators
Video
00:11:41
Knowledge Check : Combinational Circuits Advanced-1
Exercise
Multiplexers and Demultiplexers
Video
00:18:58
Universal Logic Gates and Tristate Buffers
Video
00:08:37
Summary & Knowledge Check
Video
00:25:42
Knowledge Check : Combinational Circuits Advanced -2
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
00:40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
00:45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
00:25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
00:13:16
Knowledge Check : Sequential Circuits Advanced -1
Exercise
Registers & Counters
Video
00:37:19
Sequence Generators & Frequency dividers
Video
00:26:02
Knowledge Check : Sequential Circuits Advanced -2
Exercise
Finite State Machine FSM - Basics
FSM
Video
00:37:39
Knowledge Check : FSM
Exercise
FSM - Advanced
Finite State Machines - Part - 1
Video
00:27:44
Finite State Machines - Part - 2
Video
00:21:43
Knowledge Check : Finite State Machines
Exercise
Memories
Memories
Video
00:25:54
Knowledge Check Memories -1
Exercise
Memories & PLD
Video
00:29:45
Knowledge Check : Memories, Glitches and PLD)
Exercise
Static Timing Analysis - STA : Introduction
Why & What is Timing Analysis?
Video
00:07:40
Types of Timing Analysis
Video
00:10:22
False Paths & Multi Cycle Paths
Video
00:19:36
STA in Design Flow
Video
00:05:24
Knowledge Check : Introduction to STA
Exercise
STA: Clock
Clock - Part -1
Video
00:17:35
Clock - Part - 2
Video
00:17:41
Knowledge Check - Clock
Exercise
STA : Timing Parameters
Timing Parameters in STA - Part-1
Video
00:15:49
Timing Parameters in STA - Part-2
Video
00:13:58
Timing Parameters in STA - Part-3
Video
00:10:24
Knowledge Check - Timing analysis Procedure
Exercise
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Video
00:18:30
Timing Analysis on Sequential Circuits - Part-2
Video
00:12:48
STA Procedure
Video
00:10:27
Knowledge Check - Timing analysis Procedure
Exercise
STA : Techniques to Improve Timing
Different Techniques to improve timing
Video
00:12:51
Knowledge Check - Techniques to Improve Timing
Exercise
Feedback Form
Feedback Form
External Link
Reference Books
STA Reference Book
PDF
Advanced Digital Reference Book
PDF
Module Test : Digital & STA
Module Test : Digital & STA
Exercise
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Verilog HDL Reference Material
Verilog HDL Reference Book
PDF
Verilog HDL - Quick Reference Guide
PDF
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
Design for Testability
6 Exercises • 53 Learning Materials
Reference Books
DFT Theory - Reference Book
PDF
Tessent Shell
PDF
Intro to Testing
Introduction to Testing and DFT
Video
00:12:51
Verification vs Testing
Video
00:03:12
Faults and Types of Testing
Video
00:07:40
Levels of Testing
Video
00:05:52
Fault Modelling
Video
00:11:38
Knowledge check: Introduction to testing
Exercise
Fault Collapsing
Fault Collapsing Part-1
Video
00:07:23
Fault Collapsing Part-2
Video
00:05:20
Fault Collapsing Part-3
Video
00:05:24
Introduction to ATPG
Introduction to ATPG
Video
00:04:56
Combinational ATPG
Video
00:05:20
D-Algorithm
Video
00:07:13
Fault Classes and Fault Simulation
Fault Classes
Video
00:14:45
Additional Fault Models part-1
Video
00:11:46
Additional Fault Models part-2
Video
00:08:02
Fault Simulation
Video
00:10:34
Knowledge check: Fault modelling
Exercise
DFT - Basics
What is DFT?
Video
00:09:50
Classification of DFT Techniques
Video
00:07:38
Structured DFT Techniques
Video
00:03:25
Knowledge check: DFT techniques
Exercise
Scan Insertion & Test Compression
Scan Insertion Part - 1
Video
00:07:17
Scan Insertion Part - 2
Video
00:03:04
Scan Insertion Part - 3
Video
00:04:44
Scan Insertion Part - 4
Video
00:05:38
Hierachical DFT Flow
Video
00:07:25
Test Compression
Video
00:14:51
Knowledge check: DFT techniques
Exercise
Boundary Scan & BIST
Boundary Scan
Video
00:33:00
JTAG vs IJTAG
Video
00:10:05
Introduction to BIST, LBIST & MBIST
Video
00:19:59
Knowledge check: DFT techniques
Exercise
Miscellaneous Concepts
Design Rule Checks
Video
00:03:04
How to improve Test Coverage
Video
00:04:21
Fault Diagnosis
Video
00:02:38
Tessent Shell Overview
Intro to Tessent
Video
00:03:37
System Modes
Video
00:03:13
TSDB Overview
Video
00:05:23
Knowledge check: Tessent shell
Exercise
Feedback Form
Feedback form
feedback_form
DFT - Labs
VPN Configuration Guide
PDF
DFT - Lab Manual
PDF
Solution to Lab 01
Video
00:10:32
Solution to Lab 02
Video
00:04:56
Solution to Lab 03
Video
00:05:12
Solution to Lab 04
Video
00:04:20
Solution to Lab 05
Video
00:02:22
Solution to Lab 06
Video
00:07:15
Solution to Lab 07
Video
00:06:49
Solution to Lab 08
Video
00:04:02
Solution to Lab 09
Video
00:08:23
Solution to Lab 10
Video
00:05:29
Solution to Lab 11
Video
00:05:23
Solution to Lab 12
Video
00:03:04
Solution to Lab 13
Video
00:09:57
Solution to Lab 14
Video
00:12:30
Solution to Lab 15
Video
00:07:25
RISC-V ISA & RV32I RTL Design
1 Exercises • 24 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
00:09:43
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:18
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:16
RISC-V ISA Part-1 ( introduction)
Video
00:10:44
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:59
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:10
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:20
RV32I Base Instructions (U type)
Video
00:17:12
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
Feedback Form
Feedback form
feedback_form
Final Test: RISC - V design
Final Test
Exercise
RISC-V Project - DFT
3 Learning Materials
RISC-V Specification
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
RISC-V RV32I Quick Reference Guide
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
Course Instructor
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