In today’s AI era, chip designers have access to AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V Open ISA, enabling them to design powerful, innovative SoCs efficiently. With these advancements, even the most complex SoCs can be realized for next-generation electronic products. However, thorough verification is critical to ensure the success of newly designed chips and systems. This makes it the perfect time for chip designers and VLSI enthusiasts to delve into ASIC verification methodologies and learn how to verify IPs, subsystems, and complete SoCs effectively. The course covers the complete spectrum of VLSI verification skills, starting with ASIC verification methodologies. It progresses to Advanced Verilog, Code Coverage, SystemVerilog, SystemVerilog Assertions (SVA), followed by Formal Verification, including FPV, formal algorithms, and equivalence checking, with detailed case studies.

The course then explores UVM - covering TB architecture, factory, phases, TLM Ports, sequences, virtual sequences and RAL, Gate-Level Simulation (GLS), Timing Verification, SDF annotation, Debugging, regression, low-power verification with UPF, Portable Stimulus Standard (PSS) for test scenario modelling, SoC verification methodology with various case studies. In addition, it also covers Python for DV automation, C programming for writing firmware SoC testcases, and Generative AI for RTL design and verification - empowering engineers with AI-assisted design and verification capabilities. 

This hands-on course ensures that the participants build strong foundations in Design Verification – functional verification, low-power and formal verification, GLS, DV automation, and SoC verification, while gaining hands-on expertise through labs, case studies, and real-world verification projects.