Executive Certification in VLSI Design for Testing
Earn an Executive Certification in DFT, mastering scan insertion, ATPG, BIST, boundary scan, JTAG, and test compression to ensure high fault coverage and first-pass silicon success. Build strong foundations in digital logic, Verilog, CMOS, synthesis, STA, and physical design, with Tcl/Python automation and an industry-standard SoC DFT project.
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Course Overview
In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing platforms like RISC-V, enabling the efficient design of powerful SoCs for next-generation products. However, ensuring testability and fault coverage is equally critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Design for Testing (DFT) methodologies—covering scan insertion, ATPG, fault modelling, BIST, boundary scan, JTAG, and advanced techniques for low-power and high-performance designs. A strong foundation in DFT ensures high-quality, reliable SoCs ready for mass production.
This course provides a comprehensive foundation in Design For Testing. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming - coding styles, FSM design, and lab exercises. It then walks you through CMOS fundamentals, Synthesis, Clock Domain Crossing, STA, Equivalence Checking, and Physical Design Flow - floor planning, placement, CTS, routing, layout compaction, and physical verification (DRC, LVS, IR drop, EM), with labs and case studies.
The Design For Testing module covers verification vs testing, scan insertion, ATPG, fault modelling, BIST, boundary Scan, Test compression, DRC & Test coverage, JTAG, DFT for Analog Macros, while automation skills are developed with Tcl and Python scripting. Students also learn version control with Git, before progressing to advanced DFT concepts and doing an industry-standard project – DFT implementation on an SoC.
Course Curriculum
20 Subjects
VLSI SoC Design
1 Exercises • 4 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Smartphone - SoC - Architecture
SoC Design
ASIC Vs FPGA
Knowledge Check : Introduction to VLSI
SoC ASIC Design Flow
5 Learning Materials
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
ASIC Design Flow - Part-2 (Architecture to RTL Design)
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
ASIC Design Flow - Part-4 (DFT to STA)
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Digital Design
8 Exercises • 26 Learning Materials
Introduction to Digital Electronics
Introduction to Digital Electronics
Number Systems and Codes
Number Systems and Codes
Assignment 1
Solution to Assignment 1
Knowledge Check : Number Systems and Codes
Logic Circuits
Logic Circuits
Assignment 2
Solution to Assignment 2
Knowledge Check: Logic Circuits
Combinational Circuits
Combinational Circuits - I
Knowledge Check : Combinational Logic Circuits - 1
Assignment 3
Solution to Assignment 3
Combinational Circuits - II
Knowledge Check : Combinational Logic Circuits - 2
Assignment 4
Solution to Assignment 4
Sequential Circuits
Sequential Circuits - I
Knowledge Check : Sequential Circuits - 1
Assignment 5
Solution to Assignment 5
Sequential Circuits - II
Knowledge Check : Sequential Circuits - 2
Assignment 6
Solution to Assignment 6
Finite State Machines
FSM
Solution to Assignment 7
Assignment 7
Knowledge Check : FSM
Feedback Form
Feedback Form
Memories
Memories
Assignment 8
Solution to Assignment 8
Knowledge Check : Memories
RISC-V Instruction Set Architecture
1 Exercises • 12 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
Linux Operating System
1 Exercises • 8 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
vi Text Editor
Knowledge check: Linux
Labs User Guide & VPN Configuration Guide
Ubuntu Installation Guide
Linux Labs User Guide
VPN_Configuration_Guide
Linux Lab Manual
Linux Lab 1 : Solution
Linux Lab 2 : Solution
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Verilog HDL Reference Material
Verilog HDL Reference Book
Verilog HDL - Quick Reference Guide
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Proceedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Styles
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Compiler Directive
Compiler Directive
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Verilog Lab Manual
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
Solution to Verilog Lab 01
Solution to Verilog Lab 02
Solution to Verilog Lab 03
Solution to Verilog Lab 04
Solution to Verilog Lab 05
Solution to Verilog Lab 06
RTL Linting
2 Learning Materials
Synopsys VC - Spyglass Lint - Tool Demo
VC Spyglass - Lint
Reference Material
VC_Spyglass_Lint
RTL Synthesis
3 Learning Materials
Synopsys DesignCompiler - Tool Demos
RTL Synthesis - Part-1
RTL Synthesis - Part-2
DC - Ultra
Logic Equivalence Checking
1 Learning Materials
Reference Material
Equivalence Checking
VLSI - Design - CMOS Fundamentals
2 Exercises • 4 Learning Materials
CMOS Fundamentals
CMOS - Lecture 1
CMOS - Lecture 2
CMOS - Lecture 3
CMOS Reference Book
CMOS Reference Book
Knowledge Check - CMOS
Knowledge Check - CMOS
Module Test : CMOS
Knowledge Check - CMOS
Foundation - Clock Domain Crossing
9 Learning Materials
Clock Domain Crossing
CDC Introduction, CDC Concerns,MTBF
MultiFlop Synchronizer, Toggle Synchronizer
Synchornization Technique for Multibit CDC Signals
Feedback Form
Sending Data from clock domain to other
CDC Analysis
CDC
Clock Domain Crossing : Reference Material
CDC
Feedback Form - Overall Experience
Feedback Form - Overall Experience
Foundation - Reset Domain Crossing
1 Learning Materials
Reference Material
RDC
VLSI - Design - Static Timing Analysis
5 Exercises • 13 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
Knowledge Check : Introduction to STA
STA: Clock
Clock - Part -1
Clock - Part - 2
Knowledge Check - Clock
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
Knowledge Check - Timing Parameters
STA : Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
Knowledge Check - Timing analysis Procedure
STA - Techniques to Improve Timing
Different Techniques to improve timing
Knowledge Check - Techniques to Improve Timing
VLSI -Verification - Design Automation Perl
2 Exercises • 10 Learning Materials
PERL Scripting
PERL Scripting - Lecture 1
Knowledge check:Perl1
PERL Scripting - Lecture 2
Knowledge check: Perl2
PERL Reference Book
PERL Reference Book
PERL Labs
Perl Labs User Guide
PERL Lab Manual
Lab 01 Solution
Lab 02 Solution
Lab 03 Solution
Lab 04 Solution
Lab 05 Solution
Python Programming
1 Exercises • 11 Learning Materials
Python Basics
Introduction to Python
Python Datatypes and Operators
Python Functions and Loops
Feedback Form
Python OOP
Python Exceptions
Python File IO Operations
Python Sequences and Methods
Python - Knowledge Check
Reference Material
Python Reference Material
Feedback Form - Overall Experience
Feedback Form - Overall Experience
Python - Labs
Python - Lab Manual
An Introduction to Git
1 Exercises • 5 Learning Materials
Introduction to VCS
Introduction to VCS
Feedback Form
Feedback Form
Introduction to Git
Introduction to Git
Branching and Merging
Branching and Merging
Knowledge Check : Git
Feedback Form - Overall Experience
Feedback Form - Overall Experience
VLSI - Physical Design - Introduction to Physical Design
1 Exercises • 9 Learning Materials
Introduction to Physical Design
Introduction to VLSI Design
Design Styles
Partitioning
Floorplanning
Placement
Clock Tree Synthesis [ CTS ]
Routing
Static Timing Analysis [ STA ]
Knowledge Check : Introduction to PD
Reference Book : Introduction to Physical Design
Introduction to Physical Design
Design for Testability
6 Exercises • 53 Learning Materials
Reference Books
DFT Theory - Reference Book
Tessent Shell
Intro to Testing
Introduction to Testing and DFT
Verification vs Testing
Faults and Types of Testing
Levels of Testing
Fault Modelling
Knowledge check: Introduction to testing
Fault Collapsing
Fault Collapsing Part-1
Fault Collapsing Part-2
Fault Collapsing Part-3
Introduction to ATPG
Introduction to ATPG
Combinational ATPG
D-Algorithm
Fault Classes and Fault Simulation
Fault Classes
Additional Fault Models part-1
Additional Fault Models part-2
Fault Simulation
Knowledge check: Fault modelling
DFT - Basics
What is DFT?
Classification of DFT Techniques
Structured DFT Techniques
Knowledge check: DFT techniques
Scan Insertion & Test Compression
Scan Insertion Part - 1
Scan Insertion Part - 2
Scan Insertion Part - 3
Scan Insertion Part - 4
Hierachical DFT Flow
Test Compression
Knowledge check: DFT techniques
Boundary Scan & BIST
Boundary Scan
JTAG vs IJTAG
Introduction to BIST, LBIST & MBIST
Knowledge check: DFT techniques
Miscellaneous Concepts
Design Rule Checks
How to improve Test Coverage
Fault Diagnosis
Tessent Shell Overview
Intro to Tessent
System Modes
TSDB Overview
Knowledge check: Tessent shell
Feedback Form
Feedback Form
DFT - Labs
VPN Configuration Guide
DFT - Lab Manual
Solution to Lab 01
Solution to Lab 02
Solution to Lab 03
Solution to Lab 04
Solution to Lab 05
Solution to Lab 06
Solution to Lab 07
Solution to Lab 08
Solution to Lab 09
Solution to Lab 10
Solution to Lab 11
Solution to Lab 12
Solution to Lab 13
Solution to Lab 14
Solution to Lab 15
Design For Testability - Advanced
Low Power Design
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