Executive Certification in VLSI Physical Design and Signoff
Earn an Executive Certification in VLSI Physical Design and Sign Off, covering SoC architecture, digital logic, Verilog, CMOS, DFT, and automation with Tcl/Python. Gain hands-on expertise in the full ASIC flow—synthesis to tape-out—along with advanced topics like signal integrity, low-power verification, and power-aware checks through labs and projects.
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Course Overview
In the AI era, chip designers are empowered with AI-powered EDA tools, silicon-proven IP libraries, and open computing solutions like RISC-V to design powerful SoCs efficiently. With these advancements, even the most complex SoCs can be implemented for next-generation electronic products. However, achieving timing closure, power optimization, and area efficiency in physical design is critical for first-pass silicon success. This is the right time for chip designers and VLSI enthusiasts to explore ASIC Physical Design methodologies—covering the complete flow from RTL to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, routing, timing analysis, power optimization, and sign-off techniques for successful tape-outs.
This course provides a comprehensive foundation in VLSI Physical design and verification. Learners begin with an overview of VLSI, Moore’s Law, SoC architecture, and design flows, followed by digital logic fundamentals such as number systems, combinational and sequential circuits, FSMs, and memory design. The course advances into practical hardware design and verification using Verilog HDL programming - coding styles, FSM design, and lab exercises. It then walks you through device physics and CMOS fundamentals, including MOSFET operation, CMOS fabrication, and circuit layout.
The DFT module covers verification vs testing, ATPG, scan insertion, and fault modelling, while automation skills are developed with Tcl and Python scripting. Students also learn version control with GIT, before progressing to the ASIC physical design flow, including floor planning, placement, CTS, routing, STA, layout compaction, and physical verification (DRC, LVS, IR drop, EM). Advanced topics such as signal integrity, low-power verification with UPF, and power-aware checks are included, ensuring learners gain end-to-end expertise from RTL coding to Chip tapeout with strong hands-on exposure through structured labs and industry-aligned projects.
Course Curriculum
25 Subjects
VLSI SoC Design
1 Exercises • 4 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
Digital Design
8 Exercises • 26 Learning Materials
Introduction to Digital Electronics
Introduction to Digital Electronics
Video
00:12:02
Number Systems and Codes
Number Systems and Codes
Video
00:37:45
Assignment 1
PDF
Solution to Assignment 1
Video
00:22:30
Knowledge Check : Number Systems and Codes
Exercise
Logic Circuits
Logic Circuits
Video
00:55:07
Assignment 2
PDF
Solution to Assignment 2
Video
00:30:12
Knowledge Check: Logic Circuits
Exercise
Combinational Circuits
Combinational Circuits - I
Video
00:28:25
Knowledge Check : Combinational Logic Circuits - 1
Exercise
Assignment 3
PDF
Solution to Assignment 3
Video
00:40:34
Combinational Circuits - II
Video
00:44:08
Knowledge Check : Combinational Logic Circuits - 2
Exercise
Assignment 4
PDF
Solution to Assignment 4
Video
00:30:42
Sequential Circuits
Sequential Circuits - I
Video
00:40:58
Knowledge Check : Sequential Circuits - 1
Exercise
Assignment 5
PDF
Solution to Assignment 5
Video
00:24:51
Sequential Circuits - II
Video
00:45:15
Knowledge Check : Sequential Circuits - 2
Exercise
Assignment 6
PDF
Solution to Assignment 6
Video
00:29:49
Finite State Machines
FSM
Video
00:37:39
Solution to Assignment 7
Video
00:45:24
Assignment 7
PDF
Knowledge Check : FSM
Exercise
Feedback Form
Feedback Form
External Link
Memories
Memories
Video
00:25:54
Assignment 8
PDF
Solution to Assignment 8
Video
00:08:28
Knowledge Check : Memories
Exercise
RISC-V Instruction Set Architecture
1 Exercises • 12 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
00:09:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
Linux Operating System
1 Exercises • 8 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
Video
01:15:00
vi Text Editor
Video
00:31:00
Knowledge check: Linux
Exercise
Labs User Guide & VPN Configuration Guide
Ubuntu Installation Guide
PDF
Linux Labs User Guide
PDF
VPN_Configuration_Guide
PDF
Linux Lab Manual
PDF
Linux Lab 1 : Solution
Video
00:08:26
Linux Lab 2 : Solution
Video
00:05:15
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Verilog HDL Reference Material
Verilog HDL Reference Book
PDF
Verilog HDL - Quick Reference Guide
PDF
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
VLSI - Physical Design : CMOS Design and Technologies
23 Learning Materials
Introduction to CMOS
CMOS : An Introduction to CMOS
Video
00:15:39
CMOS : MOS Fundamentals - Part 1
Video
00:15:58
CMOS : MOS Fundamentals - Part 2
Video
00:20:21
CMOS : MOS Fundamentals - Part 3
Video
00:11:39
CMOS - MOS Characteristics
CMOS : MOS - IV Characteristics : Part 1
Video
00:16:06
CMOS : MOS - IV Characteristics : Part 2
Video
00:07:16
CMOS : MOS - IV Characteristics : Part 3
Video
00:13:35
CMOS - Various Designs
CMOS : Inverter Design - Part 1
Video
00:15:29
CMOS : Inverter Design - Part 2
Video
00:21:39
CMOS : Inverter Design - Part 3
Video
00:14:32
CMOS : Combinational Circuits - Part 1
Video
00:13:26
CMOS : Combinational Circuits - Part 2
Video
00:16:21
CMOS : Logical Effort
Video
00:20:32
CMOS Layout and Stick Diagrams
CMOS : Layout Design - Part 1
Video
00:15:55
CMOS : Layout Design - Part 2
Video
00:07:53
CMOS : Stick Diagrams
Video
00:21:34
CMOS : Alternatives to CMOS
CMOS : Alternatives to CMOS - Part 1
Video
00:13:01
CMOS : Alternatives to CMOS - Part 2
Video
00:15:34
CMOS : Alternatives to CMOS - Part 3
Video
00:16:31
CMOS Labs
PD_Tanner_Tool_video_1
Video
00:20:58
PD_Tannner_Tool_Video_2
Video
00:38:10
PD_Tanner_Tool_Video_3
Video
00:27:24
Tanner Tool Lab Manual
PDF
Foundation - Design for Testability
1 Exercises • 11 Learning Materials
DFT Basics
Introduction to DFT
Video
00:11:15
Basic Testing Principles
Video
00:11:39
Feedback Form
External Link
Fault Collapsing
Video
00:12:27
What is DFT?
Video
00:10:50
DFT Techniques- Structured Techniques
Video
00:09:15
Knowledge check: DFT techniques
Exercise
Tessent Shell - Introduction
Introduction to Tessent Shell
Video
00:03:37
System Modes
Video
00:03:13
Project - Demo
Introduction_dft_structured_techniques
Video
00:01:02
Scan_chain_insertion
Video
00:07:43
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
VLSI - Physical Design - Tcl
1 Exercises • 15 Learning Materials
Introduction to Tcl
Introduction to Tcl-1
PDF
Introduction to TCL-2
PDF
Introduction to Tcl
Video
00:15:29
Control Flow Statements
Video
00:26:25
Procedures
Video
00:17:05
Data types - Strings
Video
00:15:16
Feedback Form
External Link
Mathematical Operators
Video
00:14:00
Datatypes - Lists
Video
00:19:45
Data types - Arrays
Video
00:11:37
Data types - Dictionaries
Video
00:10:22
Practice Applications
Video
00:11:46
Tcl : Knowledge Check
Exercise
TCL
Video
00:05:45
Tcl Manual
Tcl manual
PDF
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Python Programming
1 Exercises • 11 Learning Materials
Python Basics
Introduction to Python
Video
00:09:07
Python Datatypes and Operators
Video
00:28:49
Python Functions and Loops
Video
00:35:50
Feedback Form
External Link
Python OOP
Video
00:32:08
Python Exceptions
Video
00:06:36
Python File IO Operations
Video
00:09:28
Python Sequences and Methods
Video
00:32:21
Python - Knowledge Check
Exercise
Reference Material
Python Reference Material
PDF
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Python - Labs
Python - Lab Manual
PDF
An Introduction to Git
1 Exercises • 5 Learning Materials
Introduction to VCS
Introduction to VCS
Video
00:07:47
Feedback Form
Feedback Form
External Link
Introduction to Git
Introduction to Git
Video
00:20:49
Branching and Merging
Branching and Merging
Video
00:03:29
Knowledge Check : Git
Exercise
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
VLSI - Physical Design - Introduction to Physical Design - V1
1 Exercises • 9 Learning Materials
Introduction to Physical Design
Introduction to VLSI Design
Video
00:06:19
Design Styles
Video
00:09:36
Partitioning
Video
00:05:12
Floorplanning
Video
00:05:34
Placement
Video
00:05:34
Clock Tree Synthesis [ CTS ]
Video
00:06:35
Routing
Video
00:04:21
Static Timing Analysis [ STA ]
Video
00:05:24
Knowledge Check : Introduction to PD
Exercise
Reference Book : Introduction to Physical Design
Introduction to Physical Design
PDF
VLSI - Physical Design : Synthesis and PDKs
2 Exercises • 18 Learning Materials
Libraries and PDKs
Libraries and PDKs- Part 1
Video
00:18:37
Libraries and PDKs - Part 2
Video
00:10:24
Synthesis
Synthesis Concepts
Video
00:16:06
Synthesis Steps
Video
00:14:29
Synthesis Varients
Video
00:10:02
Libraries, Synthesis and PDKs : Reference Material
Synthesis : Reference Material
PDF
Libraries and PDKs : Reference Material
PDF
SDC : Reference Material
PDF
Synopsys Design Compiler ( SDC )
SDC Fundamentals
Video
00:08:44
Object Access Commands
Video
00:11:50
Understanding SDC - Break down sections and System Interfaces
Video
00:03:19
Set Driving Cells and Set Load Commands
Video
00:03:09
Clock Types - Timing Constraints and Design Rule Constraints
Video
00:08:38
Commands to create different types of clocks
Video
00:05:25
Defining Input and Output delays
Video
00:15:27
Clock Domain Crossing and Timing Exceptions
Video
00:09:16
Maximum Delay and Power Optimization Commands
Video
00:11:18
Knowledge Check : Synthesis and PDKs
Exercise
Feedback Form - PD
Feedback Form - PD Theory & Labs
External Link
Module Test : Intro to PD, CMOS , Synthesis & PDK and DFT
Module Test : Intro to PD, CMOS , Synthesis & PDK andDFT
Exercise
VLSI - Physical Design - Static Timing Analysis - V1
2 Exercises • 15 Learning Materials
Timing Analysis, STA, DTA , False path and Multicycle Path
Timing Analysis, STA, DTA, FalsePath, Multicycle Path
Video
02:07:28
STA in Digital Design Flow, Inputs and Outputs of STA Tools
Video
00:40:53
Clocks , Different Types of clocks, Uncertainties with the Clock
Clocks , Different Types of Clocks, Uncertainties With the Clock
Video
01:22:59
Timing Parameters In STA
Timing Parameters In STA
Video
00:54:09
Recovery and Removal Times and PVT Corners and their effect on Cell Delays
Video
01:49:58
Setup and Hold Times
Setup and Hold Times
Video
01:20:54
Setup and Hold In Equality Equations
Video
01:21:10
What is Prime Time
What is PrimeTime
Video
01:57:06
PrimeTime Lab Manual
Video
00:06:30
OCV and CRPR
OCV and CRPR
Video
01:23:41
Modelling of CMOS Logic Cells
Modelling of CMOS Logic Cells
Video
01:16:29
Different Techniques to improve timing
Different Techniques to improve timing
Video
01:51:11
Knowledge Check : STA
Exercise
STA : Reference Material
STA: Reference Material
PDF
STA Assignment
STA Assignment 1
PDF
STA Assignment 2
PDF
Module Test 2 : STA, SDC, Primetime
Module Test 2 : STA, SDC, Primetime
Exercise
VLSI - Physical Design - Primetime - Tool Demo and Lab Solutions - V1
1 Exercises • 43 Learning Materials
Reference Material
STA Labs Refernce Material
PDF
Primetime Tool Demo
Introduction to Primetime Tool
Video
00:07:04
STA Process
Video
00:04:59
PrimeTime in the implementation flow
Video
00:07:37
Timing Analysis Flow in PrimeTime
Video
00:04:18
How to read and interpret the timing reports (Part-1)
Video
00:04:39
How to read and interpret the timing reports (Part-2)
Video
00:11:39
How to invoke PrimeTime and use it?
Video
00:09:06
How to setup PT Tool with various inputs?
Video
00:08:37
How to write tcl scripts to automate loading the inputs and report generation?
Video
00:05:27
How to run various reporting commands?
Video
00:10:30
How to use GUI and understand histogram?
Video
00:05:20
STA Lab Manual
PrimeTime Lab Manual
PDF
Primetime : Lab 01
Task_1_Restore_a_Prime_Time_Session
Video
00:09:45
Task_2_ Explore_some_helpful_commands
Video
00:07:00
Task_3_Validate_an_Existing_Prime_Time_Session
Video
00:08:37
Task_4_ Execute_the_Run_Script_and_Analyze_the_run
Video
00:08:15
Task_5_Analyze_STA_Reports
Video
00:10:48
Primetime : Lab 02
Task_1_validate_constraints
Video
00:07:39
Task_2_Analyse_Timing_Report_for_Input_Delay_Constraint
Video
00:10:11
Task_3_Analyse_Timing_Report_for_Output_Delay_Constraint
Video
00:07:08
Primetime : Lab 03
Task_1_Setup_PrimeTime_for_Lab3
Video
00:03:51
Task_2_Generate_Summary_Reports
Video
00:12:27
Task_3_Analyse_Timing_Reports_for_Setup_and_Hold
Video
00:12:36
Task_4_ Apply_the_Correct_Timing_Report_Switches
Video
00:08:04
Task_5_Identify_Half-Clock_Cycle_Paths
Video
00:06:50
Primetime : Lab 04
Task 1 - Get to Know the Design Clocks
Video
00:14:01
Task 2 - Use the GUI to Report Clock Relationships
Video
00:18:11
Task 3 - Use the GUI to explore detail of timing paths
Video
00:11:15
Task 4 - Report a false violations
Video
00:10:00
Task 5 - Re-execute the run script to reduce violations
Video
00:03:10
Primetime : Lab 05
Lab5 - Task1
Video
00:09:19
Lab5 - Task2
Video
00:16:04
Primetime : Lab 06
Lab 06 : Task 1
Video
00:03:44
Lab 06 : Task 2
Video
00:03:32
Lab 06 : Task 3
Video
00:05:49
Lab 06 : Task 4
Video
00:03:56
Primetime : Lab 07
Lab 07 : Task 1
Video
00:04:14
Lab 07 : Task 2
Video
00:15:34
Lab 07 : Task 3
Video
00:02:43
Primetime : Lab 08
Lab 08 : Task 1
Video
00:08:20
Lab 08 : Task 2
Video
00:11:27
Lab 08 : Task 3
Video
00:03:06
Knowledge Check : Primetime
Knowledge Checks : Primetime
Exercise
VLSI - Physical Design : Floor Planning and Power Planning
2 Exercises • 9 Learning Materials
Floor Planning
Introduction to Floor Planning
Video
00:15:19
Floor Planning : Aspect Ratio Utilization
Video
00:15:08
Floor Planning : Macros
Video
00:17:29
Floor Planning : Blockages
Video
00:13:19
Knowledge Check : Floor planning
Exercise
Power Planning
Introduction to Power Planning
Video
00:14:31
Power Planning : Regions, Patterns, Extensions
Video
00:08:54
Power Planning : Mesh Pattern
Video
00:16:38
Power Planning : Strageic Connection
Video
00:21:46
Power planning : PNA
Video
00:05:21
Knowledge Check : Power planning
Exercise
VLSI - Physical Design : Placement
1 Exercises • 20 Learning Materials
Placement
Placement : An Introduction
Video
00:04:42
Goals of Placement
Video
00:13:11
Placement : Cost Components and flow
Video
00:15:13
Detailed Placement
Video
00:02:44
Congestion and Overflow
Video
00:21:05
Timing driven placement and strategies
Video
00:14:42
HFNS and Cloning
Video
00:09:58
Scan Chain Reordering
Video
00:07:57
Placement Qualification and Outputs
Video
00:07:40
Knowledge Check : Placement
Exercise
Placement Flow Overview
PDF
Fusion Compiler : Lab 07
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:41
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:57
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:52
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:57
VLSI - Physical Design : Clock Tree Synthesis
5 Learning Materials
Clock Tree Synthesis
Clock Tree Synthesis - An Introduction
Video
00:09:52
Pre CTS
Video
00:18:26
CTS : What is clock
Video
00:07:03
CTS Cell Selection
Video
00:18:26
Clock Tree Synthesis : Reference Material
CTS : Reference Material
PDF
VLSI - Physical Design : Routing
2 Exercises • 4 Learning Materials
Routing
Routing : An Introduction
Video
00:14:55
Routing : Global Routing
Video
00:25:38
Routing : Detail Routing
Video
00:17:12
Knowledge Check: Routing
Exercise
Routing : Reference Material
Routing : Reference Material
PDF
Module Test 3: Floorplanning, Powerplanning, Placement, CTS, Routing
Module test 3: Floorplanning, Powerplan, Placement, CTS, Routing
Exercise
VLSI - Physical Design - Fusion Compiler (Design Planning) : Tool Demo and Labs
50 Learning Materials
Introduction to Fusion Compiler
Fusion Compiler : Compile Flow
Video
00:14:51
Physical Design Using Fusion Compiler Lab Manual
Fusion Compiler Lab Manual
PDF
Fusion Compiler : Lab 01
Fusion Compiler : Introduction
Video
00:21:45
Fusion Compiler: Design Planning - Lab 01 : Task 02
Video
00:03:03
Fusion Compiler : Design Planning - Lab 01 : Task 03
Video
00:09:30
Fusion Compiler : Design Planning - Lab 01 : Task 04 to Task 06
Video
00:05:53
Fusion Compiler : Design Planning - Lab 01 : Task 07
Video
00:05:33
Fusion Compiler : Design Planning - Lab 01 : Task 08
Video
00:04:34
Fusion Compiler : Design Planning - Lab 01 : Task 09
Video
00:09:02
Fusion Compiler : Design Planning - Lab 01 : Task 10 & Task 11
Video
00:12:24
Fusion Compiler : Lab 02
Fusion Compiler : Design Creation ( Reading RTL)
Video
00:19:22
Fusion Compiler : DMM
Video
00:10:09
Fusion Compiler : Design Planning - Lab 02 : Task 01
Video
00:05:30
Fusion Compiler : Design Planning - Lab 02 : Task 02
Video
00:22:48
Fusion Compiler : Design Planning - Lab 02 : Task 03
Video
00:10:26
Fusion Compiler : Design Planning - Lab 02 : Task 04
Video
00:07:32
Fusion Compiler : Lab 03
Compile_Flow
Video
00:14:51
Fusion Compiler : Design Planning - Lab 03 : Task 1
Video
00:03:56
Fusion Compiler : Design Planning - Lab 03 : Task 2
Video
00:06:07
DFT_Flow
Video
00:03:15
Fusion Compiler : Design Planning - Lab 03 : Task 3
Video
00:07:12
Fusion Compiler : Design Planning - Lab 03 : Task 4
Video
00:05:16
Fusion Compiler : Design Planning - Lab 03 : Task 5
Video
00:10:21
Fusion Compiler : Design Planning - Lab 03 : Task 6
Video
00:17:15
Fusion Compiler : Design Planning - Lab 03 : Task 7
Video
00:14:08
Fusion Compiler : Design Planning - Lab 03 : Task 8
Video
00:07:25
Fusion Compiler : Lab 04
Fusion Compiler : Design Planning - Lab 04 : Task 5
Video
00:19:08
Technology Setup
Video
00:17:02
Fusion Compiler : Design Planning - Lab 04 : Task 1
Video
00:05:33
Fusion Compiler : Design Planning - Lab 04 : Task 2
Video
00:08:36
Fusion Compiler : Design Planning - Lab 04 : Task 3
Video
00:05:51
Auto_Floorplan
Video
00:19:05
Fusion Compiler : Design Planning - Lab 04 : Task 4
Video
00:07:32
MCMMM - Part 1
Video
00:29:51
MCMMM - Part 2
Video
00:18:44
Fusion Compiler : Lab 05
CCD - Part 1
Video
00:21:03
CCD - Part 2
Video
00:07:08
CCD - part 3
Video
00:18:16
Fusion Compiler : Design Planning - Lab 05 : Task 1
Video
00:13:17
Fusion Compiler : Design Planning - Lab 05 : Task 2
Video
00:11:19
Fusion Compiler : Design Planning - Lab 05 : Task 3
Video
00:15:20
Fusion Compiler : Design Planning - Lab 05 : Task 4
Video
00:07:38
Fusion Compiler : Lab 06
ICGs - Part 1
Video
00:17:05
ICGs - Part 2
Video
00:18:21
ICGs - Part 3
Video
00:07:05
ICGs - Part 4
Video
00:16:32
ICGs - Part 5
Video
00:12:37
Fusion Compiler : Design Planning - Lab 06 : Task 1
Video
00:25:10
Fusion Compiler : Design Planning - Lab 06 : Task 2
Video
00:15:46
Fusion Compiler : Design Planning - Lab 06 : Task 3
Video
00:09:23
VLSI - Physical Design - Fusion Compiler ( Design Implementation) : Tool Demo and Labs
1 Exercises • 35 Learning Materials
Introduction to Design Implementation
Fusion Compiler : Design Implementation
Video
00:05:30
Fusion Compiler : Lab 07
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:41
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:57
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:52
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:57
Fusion Compiler : Lab 08
Fusion Compiler : Design Implementation - Lab 08A : Task 1
Video
00:12:26
Fusion Compiler : Design Implementation - Lab 08A : Task 2
Video
00:23:02
Fusion Compiler : Design Implementation - Lab 08A - Task 3
Video
00:14:29
Fusion Compiler : Design Implementation - Lab 08A - Task 4
Video
00:10:16
Fusion Compiler : Design Implementation - Lab 08A - Task 5
Video
00:13:16
Fusion Compiler : Design Implementation - Lab 08B - Task 1
Video
00:23:25
Fusion Compiler : Design Implementation - Lab 08B - Task 2
Video
00:07:20
Fusion Compiler : Design Implementation - Lab 08B - Task 3
Video
00:03:02
Fusion Compiler : Design Implementation - Lab 08B - Task 4
Video
00:03:02
Fusion Compiler : Design Implementation - Lab 08B - Task 5
Video
00:21:55
Fusion Compiler : Design Implementation - Lab 08B - Task 6
Video
00:17:31
Fusion Compiler : Design Implementation - Lab 08B - Task 8
Video
00:11:36
Fusion Compiler : Lab 09
Fusion Compiler : Design Implementation - Lab 09 - Task 1
Video
00:06:14
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 1
Video
00:20:51
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 2
Video
00:14:25
Fusion Compiler : Lab 10 - Sign off
Signoff
Video
00:05:49
ECO Flow
Video
00:03:07
ECO Flow In Fusion Compiler
Video
00:00:36
Timing ECOs
Video
00:02:24
Spare Cells
Video
00:00:53
Manual ECO Vs Automated ECOs
Video
00:02:12
ECO Fusion Work Flow
Video
00:04:16
Signoff_ECO_Flow
PDF
Knowledge Check : Signoff / ECO
Exercise
Fusion Compiler : Lab 10 - Task 1 & 2
Video
00:22:44
Logic Equivalence Checking
1 Learning Materials
Reference Material
Equivalence Checking
PDF
VLSI - Physical Design : Signal Integrity and Cross Talk
8 Learning Materials
Signal Integrity and Crosstalk
Introduction to SI and CT
Video
00:07:52
Reasons for Signal Integrity and Crosstalk
Video
00:13:51
Impact of Lateral and Interlayer Capacitance
Video
00:13:30
Understanding the Noise Margin
Video
00:15:54
Crosstalk Effects
Video
00:05:59
Crosstalk Mechanisms
Video
00:07:15
Noise Protection Techniques for SI and CT
Video
00:12:32
Signal Integrity and Crosstalk : Reference Material
Signal Integrity and Crosstalk : Reference Material
PDF
Noise Analysis and Layout COmpaction
Foundation - UPF for Low Power
VLSI - Physical Design : Physical Verification
2 Exercises • 22 Learning Materials
Physical Verification : An Introduction
Physical Verification : Introduction
Video
00:10:05
Physical Verification : DRC
Video
00:12:23
Physical Verification : LVS
Video
00:08:55
Physical Verification : PERC - Part 1
Video
00:11:41
Physical Verification : PERC - Part 2
Video
00:15:21
Physical Verification : PERC - Part 3
Video
00:22:12
Physical Verification : PERC - Part 4
Video
00:13:13
Physical Verification : PERC - Part 5
Video
00:14:09
Knowledge Check - Physical Verification
Exercise
Physical Verification : Reference Material
Physical Verification : DRC & LVS - Reference Material
PDF
Physical verification : Calibre PERC - Reference Material
PDF
Physical Verification Labs
Physical Verification Using Calibre Tool - Lab Manual
PDF
Introduction to Calibre GUI
Video
01:06:07
Calibre - Lab 1
Video
00:32:48
Calibre - lab 2
Video
00:23:04
Calibre - Lab 3 & 4
Video
00:18:13
Calibre Tool Demo - Physical Verification
Video
00:05:30
Calibre Tool Demo - Design Rules
Video
00:12:56
Calibre Tool Demo - Calibre DRC Flow
Video
00:05:04
Calibre Tool Demo - Solving DRC using Calibre nmdrc tool
Video
00:05:27
Calibre Tool Demo - Layout Versus Schematic
Video
00:06:01
Calibre Tool Demo -Calibre nmlvs Flow
Video
00:11:46
Feedback Form - PD Theory & Labs
Feedback Form - PD Theory & Labs
External Link
Module test 4 : SI & CT, Signoff, ECO and Physical Verification
Module test 4 : SI & CT, Signoff, ECO and Physical Verification
Exercise
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