Executive Certification in RISC-V IP Design
Earn an Executive Certification in RISC-V IP Design covering CPU Design, RISC-V ISA, Verilog/SystemVerilog design, RTL linting, Formal Verification, Logic Synthesis, Equivalence Checking, Low-Power Design, CDC/RDC, and case studies. Gain hands-on experience with a RISC-V IP project to master the design of complex CPUs and IPs.
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Course Overview
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor.
This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn CPU architecture, RISC-V IP Design using Verilog and SystemVerilog, RTL Linting, Logic Synthesis, Equivalence Checking, Low Power design, Clock Domain Crossing and Reset Domain Crossing, with various Case Studies.
In this course, you will design a multi-stage RISC-V Pipeline Processor – exploring RTL IP design using SystemVerilog and IP verification using formal verification and UVM RISC-V VIP. This project experience will help you deal with designing any complex CPUs and IPs.
Course Curriculum
20 Subjects
RISC-V Processor Architecture
9 Exercises • 41 Learning Materials
RISC-V Overview
RISC-V Overview
RISC-V Overview Knowledge Check
RISC-V Open ISA
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V - Open ISA
RISC-V ISA
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
RISC-V Base ISA
Base ISA
RV 32I Instructions
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V Extensions
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
RISC-V M Extensions
RISC-V A Extension
RISC-V C-Extension - Part-1 (Introduction to C Extension)
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Knowledge Check : RISC-V Extensions
RISC-V privileged ISA
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
RISC-V - Privileged ISA
RISC-V Machine ISA
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
RISC-V Machine ISA
RISC-V Supervisor ISA
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Knowledge Check : Supervisor ISA
Case Study: RISC-V Operating System
RISC-V OS - Overview
RISC-V OS - Booting Process
RISC-V OS - Paging
RISC-V OS - Kernel Traps
RISC-V OS - User Traps
RISC-V Hypervisor ISA
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Hypervisor - Part-4 (VS Mode CSR's)
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Knowledge Check : Hypervisor ISA
PMA and PMP
RISC-V PMA and PMP
Knowledge Check : PMA and PMP
RISC-V Debug
1 Exercises • 4 Learning Materials
Debug
RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)
RISC-V Debug - Part - 2 (RISC-V Debug System)
RISC-V Debug - Part - 3 (RISC-V Debug CSR's)
RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)
Knowledge Check : RISC-V Debug
RISC-V PLIC
1 Exercises • 2 Learning Materials
PLIC
PLIC Part -1 (Introduction to PLIC)
PLIC Part -2 (Operation of PLIC and various Registers in PLIC)
Knowledge Check : RISC-V PLIC
RISC-V Software Interfaces and Programming
4 Exercises • 13 Learning Materials
Application Binary Interface (ABI)
ABI_V1(Introduction to ABI)
ABI_V2 (RISC-V Calling Conventions Part-1)
ABI_V3 (RISC-V Calling Conventions Part-2)
ABI_V4 (RISC-V Calling Conventions Part-3)
ABI_V5 (RISC_V ELF Specifications)
ABI_V6 (RISC-V Linker Relaxation)
Knowledge Check : Application Binary Interface (ABI)
Supervisor Binary Interface (SBI)
SBI_V1 (Introduction to SBI)
SBI_V2 (Case Study on Open SBI)
SBI_V3 (SBI Extensions)
Knowledge Check : Supervisor Binary Interface (SBI)
RISC-V Assembly Programming
RISC-V Assembly Programming Part-1 (Assembly Syntax)
RISC-V Assembly Programming Part-1 (Assembly Examples)
Knowledge Check : RISC-V Assembly Programming
RISC-V Toolchain
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Knowledge Check : RISC-V Toolchain
RISC-V Caches
1 Exercises • 5 Learning Materials
Cache Memory
Memory Hierarchy
Cache Introduction
Cache Associativity
Cache Policies
Cache Coherency
Knowledge Check : Caches
Virtual Memory Management
1 Exercises • 8 Learning Materials
Virtual Memory Management
VMM Introduction
Memory Concerns
Virtual Memory
Page Table
Address Translation
TLB
Summary
Knowledge Check : Virtual Memory Management
TLB
CPU Architecture and Pipelined Design
RISC-V Processor IP RTL Design
2 Exercises • 11 Learning Materials
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Verilog HDL Reference Material
Verilog HDL Reference Book
Verilog HDL - Quick Reference Guide
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Proceedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Styles
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Compiler Directive
Compiler Directive
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Verilog Lab Manual
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
Solution to Verilog Lab 01
Solution to Verilog Lab 02
Solution to Verilog Lab 03
Solution to Verilog Lab 04
Solution to Verilog Lab 05
Solution to Verilog Lab 06
VLSI - Design - Advanced Verilog&Code Coverage
5 Exercises • 17 Learning Materials
Advanced Verilog
Timescale system task & localparm
Generate block & Continuous Procedural Assignments
Knowledge Check- Advance Verilog 1
Self checking testbench and Automatic Tasks
Named Events and Stratified Event Queue
Knowledge Check- Advance Verilog 2
Knowledge Check : Design Compiler
Knowledge Check: RTL Linting
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
Code Coverage
Definition of Code Coverage
Statement and branch coverage
Condition & Expression Coverage
Toggle & FSM Coverage
Questasim commands for Code Coverage
Makefile for Simulations
Knowledge Check-Code Coverage 1
Code Coverage - Reference Book
Code Coverage Reference Book
Advanced Verilog & Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
Advanced Verilog & Code Coverage Lab Manual - Questasim
Advanced Verilog Lab Solutions Lab 1 & 2
Code Coverage Lab Solutions Lab 3, 4 & 5
Router Project - Specification
Router_1x3_design - Specification
RTL Linting
2 Learning Materials
Synopsys VC - Spyglass Lint - Tool Demo
VC Spyglass - Lint
Reference Material
VC_Spyglass_Lint
RTL Synthesis
3 Learning Materials
Synopsys DesignCompiler - Tool Demos
RTL Synthesis - Part-1
RTL Synthesis - Part-2
DC - Ultra
Logic Equivalence Checking
1 Learning Materials
Reference Material
Equivalence Checking
Foundation - Clock Domain Crossing
9 Learning Materials
Clock Domain Crossing
CDC Introduction, CDC Concerns,MTBF
MultiFlop Synchronizer, Toggle Synchronizer
Synchornization Technique for Multibit CDC Signals
Feedback Form
Sending Data from clock domain to other
CDC Analysis
CDC
Clock Domain Crossing : Reference Material
CDC
Feedback Form - Overall Experience
Feedback Form - Overall Experience
Foundation - Reset Domain Crossing
1 Learning Materials
Reference Material
RDC
Low Power Design
SystemVerilog For RTL Design
1 Exercises • 12 Learning Materials
SV for RTL Design
Introduction_to_SV_for_design
Data_types
Operators
Procedural_blocks
Procedural_statements
Feedback Form
Tasks and Functions
Packages
Arrays
Interfaces
SV for RTL Design - Knowledge check
Case Study
Case study
Feedback Form - Overall Experience
Feedback Form - Overall Experience
Verification Methodology Overview
2 Exercises • 15 Learning Materials
Verification Methodology
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Constraint Random Coverage Driven Verification
Feedback Form
Verification Methodologies & Summary
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Transactions
SV Interface
SV Virtual Interface
SV OOP
SV Randomization & Functional Coverage
SV TB Architecture
Knowledge Check : SV language Concepts Overview
VLSI -Verification - Assertion Based Verification-SVA
6 Exercises • 21 Learning Materials
SVA Reference Book
SVA Reference Book
SVA Introduction & Types of Assertions
What are Assertions?
Necessity of using SystemVerilog Assertions
Types of Assertions
SVA - Knowledge Check - 1
SVA Building Blocks, System Functions
SVA Building Blocks
System Functions
SVA - Knowledge Check - 2
Writing Sequences and Implication Operators
How to write sequences?
Exercise based on Implication Operators and Timing Windows
Implication Operators
SVA - Knowledge Check - 3
Repetition Operators and Sequence Composition
Repetition Operators
Sequence Composition
Methods for Sequences
SVA - Knowledge Check - 4
Miscellaneous Concepts and Connecting Assertions to DUT
Miscllenious Cocenpts in SVA
Connecting Assertions to DUT
SVA - Knowledge Check - 5
Knowledge Check : SVA
Knowledge Checks : SVA
SVA Labs
SVA_Labs_User_Guide
SVA Lab Solution
SVA Lab Manual - Synopsys VCS
SVA Case Study
Explanation to Project Specification
Alarm Clock Project Specification
SVA Assignments
SVA Assignment
Solution to SVA Assignment
Formal Verification
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