The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor.

This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn CPU architecture, RISC-V IP Verification using SystemVerilog and UVM, ASIC Verification Methodologies, Formal Verification, Low Power Verification, Portable Stimulus Standard, with various Case Studies.

In this course you will verify a multi-stage RISC-V Pipeline Processor – exploring RTL IP verification using formal verification,  SystemVerilog, UVM, and RISC-V CPU compliance testing. This project experience will help you deal with verifying any complex RISC-V CPUs and IPs, and creating Verification IPs.