Executive Post Graduate Certification in VLSI SoC Design and Verification
Earn an Executive Certification through the VLSI SoC Design and Verification course, covering RISC-V and ARM ISA, SoC architecture, RTL design and ASIC Verification, and various interface protocols (AXI, AHB, APB, SPI, UART, I2C, GPIO), Portable Stimulus, and low-power design with case studies. Gain hands-on experience with a RISC-V SoC project to master the design and verification of complex SoCs.
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Course Overview
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture] - open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and SoCs with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V SoC.
This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs, RISC-V Standard Extensions, Interrupts, PMP, and RISC-V Debug. Also, as part of this hands-on course, you will learn ARM ISA, SoC architecture, SoC Design Methodology, RISC-V SoC RTL Design using Verilog and SystemVerilog, RISC-V SoC RTL Verification using UVM, SoC interface protocols - AMBA [AXI, AHB, APB], SPI, UART, I2C, GPIO, Portable stimulus standard, Low power design and verification, with various Case Studies.
In this course, you will design and verify a RISC-V SoC – exploring SoC RTL design using Verilog and SystemVerilog, SoC RTL verification using UVM. Also, you will implement the SoC - exploring ASIC design flow - Synthesis, DFT, and PD. This project experience will help you deal with designing any complex SoCs.
Course Curriculum
27 Subjects
VLSI SoC Design
1 Exercises • 4 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
SoC ASIC Design Flow
5 Learning Materials
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
RISC-V SoC Design - Methodology, Process & Fabrication
6 Learning Materials
RISC-V SoC Design - Methodology, Process and Fabrication
Microcontrollers Vs Complex SoCs
Video
00:23:06
Computer System Architecture - Von Neuman Vs Harvard
Video
00:21:52
SoC Design Considerations and RISC-V ISA Overview
Video
00:22:02
RISC-V Toolchain, CPU, and Memories - Physical Vs Virtual
Video
00:15:08
MMUs and Interrupt Controllers
Video
00:17:50
SoC Design - PPA, SoC Manufacturing and Packaging
Video
00:13:41
Memories and Memory Controllers
4 Learning Materials
Memories and Memory Controllers
Introduction to Memories
Video
00:05:07
Volatile Memories
Video
00:27:32
Non-Volatile Memories
Video
00:12:24
Memory Controllers
Video
00:11:01
RISC-V Caches
1 Exercises • 5 Learning Materials
Cache Memory
Memory Hierarchy
Video
00:03:40
Cache Introduction
Video
00:06:13
Cache Associativity
Video
00:07:09
Cache Policies
Video
00:04:19
Cache Coherency
Video
00:14:58
Knowledge Check : Caches
Exercise
Operating Systems
2 Learning Materials
Operating Systems
Introduction to Operating Systems
Video
00:14:31
Features of OS
Video
00:34:50
Virtual Memory Management
1 Exercises • 8 Learning Materials
Virtual Memory Management
VMM Introduction
Video
00:01:42
Memory Concerns
Video
00:03:01
Virtual Memory
Video
00:03:38
Page Table
Video
00:06:17
Address Translation
Video
00:14:06
TLB
Video
00:11:01
Summary
Video
00:03:39
Knowledge Check : Virtual Memory Management
Exercise
TLB
Video
00:11:15
RISC-V Processor Architecture
9 Exercises • 41 Learning Materials
RISC-V Overview
RISC-V Overview
Video
00:09:42
RISC-V Overview Knowledge Check
Exercise
RISC-V Open ISA
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V - Open ISA
Exercise
RISC-V ISA
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
RISC-V Base ISA
Base ISA
Video
00:15:06
RV 32I Instructions
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V Extensions
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
Video
00:15:16
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
Video
00:17:12
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
Video
00:14:57
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
Video
00:06:10
RISC-V M Extensions
Video
00:09:13
RISC-V A Extension
Video
00:16:28
RISC-V C-Extension - Part-1 (Introduction to C Extension)
Video
00:12:07
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Video
00:08:47
Knowledge Check : RISC-V Extensions
Exercise
RISC-V privileged ISA
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Video
00:15:04
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
Video
00:13:39
RISC-V - Privileged ISA
Exercise
RISC-V Machine ISA
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Video
00:15:34
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Video
00:22:36
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Video
00:16:29
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
Video
00:09:45
RISC-V Machine ISA
Exercise
RISC-V Supervisor ISA
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Video
00:14:57
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Video
00:15:48
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Video
00:21:12
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Video
00:19:09
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Video
00:03:34
Knowledge Check : Supervisor ISA
Exercise
Case Study: RISC-V Operating System
RISC-V OS - Overview
Video
00:09:29
RISC-V OS - Booting Process
Video
00:17:03
RISC-V OS - Paging
Video
00:18:27
RISC-V OS - Kernel Traps
Video
00:14:24
RISC-V OS - User Traps
Video
00:18:55
RISC-V Hypervisor ISA
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Video
00:11:01
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Video
00:12:20
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Video
00:07:45
Hypervisor - Part-4 (VS Mode CSR's)
Video
00:07:58
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Video
00:05:34
Knowledge Check : Hypervisor ISA
Exercise
PMA and PMP
RISC-V PMA and PMP
Video
00:18:04
Knowledge Check : PMA and PMP
Exercise
RISC-V Debug
1 Exercises • 4 Learning Materials
Debug
RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)
Video
00:05:23
RISC-V Debug - Part - 2 (RISC-V Debug System)
Video
00:07:22
RISC-V Debug - Part - 3 (RISC-V Debug CSR's)
Video
00:07:00
RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)
Video
00:18:54
Knowledge Check : RISC-V Debug
Exercise
RISC-V PLIC
1 Exercises • 2 Learning Materials
PLIC
PLIC Part -1 (Introduction to PLIC)
Video
00:13:25
PLIC Part -2 (Operation of PLIC and various Registers in PLIC)
Video
00:19:02
Knowledge Check : RISC-V PLIC
Exercise
RISC-V Software Interfaces and Programming
4 Exercises • 13 Learning Materials
Application Binary Interface (ABI)
ABI_V1(Introduction to ABI)
Video
00:06:54
ABI_V2 (RISC-V Calling Conventions Part-1)
Video
00:32:44
ABI_V3 (RISC-V Calling Conventions Part-2)
Video
00:12:09
ABI_V4 (RISC-V Calling Conventions Part-3)
Video
00:14:45
ABI_V5 (RISC_V ELF Specifications)
Video
00:41:30
ABI_V6 (RISC-V Linker Relaxation)
Video
00:06:09
Knowledge Check : Application Binary Interface (ABI)
Exercise
Supervisor Binary Interface (SBI)
SBI_V1 (Introduction to SBI)
Video
00:20:30
SBI_V2 (Case Study on Open SBI)
Video
00:01:51
SBI_V3 (SBI Extensions)
Video
00:32:46
Knowledge Check : Supervisor Binary Interface (SBI)
Exercise
RISC-V Assembly Programming
RISC-V Assembly Programming Part-1 (Assembly Syntax)
Video
00:27:34
RISC-V Assembly Programming Part-1 (Assembly Examples)
Video
00:45:38
Knowledge Check : RISC-V Assembly Programming
Exercise
RISC-V Toolchain
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
Video
00:34:12
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Video
00:33:33
Knowledge Check : RISC-V Toolchain
Exercise
RISC-V Processor IP RTL Design
2 Exercises • 11 Learning Materials
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Verilog HDL Reference Material
Verilog HDL Reference Book
PDF
Verilog HDL - Quick Reference Guide
PDF
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
VLSI - Design - Advanced Verilog and Code Coverage
5 Exercises • 17 Learning Materials
Advanced Verilog
Timescale system task & localparm
Video
00:14:48
Generate block & Continuous Procedural Assignments
Video
00:18:37
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
00:15:34
Named Events and Stratified Event Queue
Video
00:19:56
Knowledge Check- Advance Verilog 2
Exercise
Knowledge Check : Design Compiler
Exercise
Knowledge Check: RTL Linting
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Questasim commands for Code Coverage
Video
00:11:26
Makefile for Simulations
Video
00:08:36
Knowledge Check-Code Coverage 1
Exercise
Code Coverage - Reference Book
Code Coverage Reference Book
PDF
Advanced Verilog & Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual - Questasim
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
00:19:05
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
00:25:16
Router Project - Specification
Router_1x3_design - Specification
PDF
RISC-V Processor IP RTL Verification
30 Exercises • 129 Learning Materials
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Questasim commands for Code Coverage
Video
00:11:26
Makefile for Simulations
Video
00:08:36
Knowledge Check-Code Coverage 1
Exercise
Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual - Questasim
PDF
Code Coverage Lab Solutions
Video
00:25:16
Code Coverage - Reference Book
Code Coverage Reference Book
PDF
Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Verification Methodologies & Summary
Video
00:27:11
Constraint Random Coverage Driven Verification
Video
00:25:37
Knowledge Check : Verification Methodology Overview
Exercise
SystemVerilog Language Concepts
SV Concepts Agenda
Video
00:06:38
SV Overview
Video
00:11:16
SV Randomization & Functional Coverage
Video
00:06:47
SV TB Architecture
Video
00:10:19
SV Interface
Video
00:14:51
SV Virtual Interface
Video
00:11:40
SV OOP
Video
00:13:56
SV Transactions
Video
00:14:46
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
00:10:50
SV Data Types - 2 State, Struct & Enum
Video
00:15:27
SV Data Types - Strings,Packages & Summary
Video
00:09:04
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
00:09:45
SV Memories - Dynamic Arrays & Queues
Video
00:07:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
00:13:19
Knowledge Check:Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
00:11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
00:09:52
Knowledge Check : Tasks & Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
00:18:44
SV Interfaces - Modports & Clocking Block
Video
00:18:30
SV Interfaces - Examples & Summary
Video
00:20:49
Knowledge Check:Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
00:15:05
SV OOP - Constructor, Null Object, Object assignments and copy
Video
00:17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
00:17:30
Knowledge Check: Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
00:20:50
SV OOP - Static properties & methods and Pass by ref
Video
00:15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
00:21:53
Knowledge Check: Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
00:10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
00:12:52
SV Randomization - Set Membership, Constraints & Summary
Video
00:13:22
Knowledge Check: Randomization
Exercise
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Video
00:23:11
Knowledge Check : Threads , Events, Semaphore & Mailbox
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
00:17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
00:15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
00:17:30
Knowledge Check : Functional Coverage
Exercise
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Video
00:10:18
Testbench Architecture and Verification Flow
Video
00:08:12
Transaction and Generator
Video
00:10:55
Interface and Drivers
Video
00:13:10
Monitors
Video
00:08:56
Scoreboard and Reference Model
Video
00:12:59
Environment and Testcases
Video
00:13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
00:10:45
SystemVerilog Labs
SystemVerilog Lab Manual
PDF
Lab 1 Solution : Data Types
Video
00:17:56
Lab 2 Solution : Interfaces
Video
00:09:26
Lab 3 Solution : OOP Basics
Video
00:08:51
Lab 4 Solution : Advanced OOP
Video
00:18:09
Lab 5 Solution : Randomization
Video
00:05:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
00:22:02
Lab 7 Solution : Transaction
Video
00:09:43
Lab 8 Solution : Transactors
Video
00:09:01
Lab 9 Solution : Scoreboard & Reference Model
Video
00:10:59
Lab 10 Solution : Environment & Testcases
Video
00:11:20
SVA Introduction & Types of Assertions
What are Assertions?
Video
00:13:07
Necessity of using SystemVerilog Assertions
Video
00:14:46
Types of Assertions
Video
00:14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks, System Functions
SVA Building Blocks
Video
00:17:34
System Functions
Video
00:11:48
SVA - Knowledge Check - 2
Exercise
Writing Sequences and Implication Operators
How to write sequences?
Video
00:11:21
Implication Operators
Video
00:24:34
Exercise based on Implication Operators and Timing Windows
Video
00:14:18
SVA - Knowledge Check - 3
Exercise
Repetition Operators and Sequence Composition
Repetition Operators
Video
00:21:46
Sequence Composition
Video
00:19:46
Methods for Sequences
Video
00:07:21
SVA - Knowledge Check - 4
Exercise
Miscellaneous Concepts and Connecting Assertions to DUT
Miscellaneous Concepts in SVA
Video
00:07:27
Connecting Assertions to DUT
Video
00:07:59
SVA - Knowledge Check - 5
Exercise
SVA Labs
SVA Labs User Guide
PDF
SVA Lab Solution
Video
00:12:05
SVA Lab Manual
PDF
SVA Reference Book
SVA Reference Book
PDF
Universal Verification Methodology Overview
Introduction to UVM
Video
00:10:47
UVM Concepts
Video
00:04:37
UVM SoC TB
Video
00:08:49
UVM AHB UVC
Video
00:07:08
UVM SoC TB Examples
Video
00:05:31
Knowledge Check : Introduction to UVM
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
00:13:48
UVM Base Class Hierarchy
Video
00:14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
00:11:19
UVM Factory - Registration Process
Video
00:06:02
UVM Factory - Create Method and Factory Overriding
Video
00:11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
00:10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
00:10:41
UVM - TB Overview
Video
00:10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
00:16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
00:13:13
UVM Reporting Mechanism
Video
00:15:01
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
00:11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
00:13:01
UVM Configuration - Introduction to Configuration Facility
Video
00:13:02
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
00:09:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
00:15:01
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
00:16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
00:11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
00:15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
00:13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
00:08:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
00:09:23
UVM Events
Video
00:09:06
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
00:09:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM Labs
UVM Lab Manual
PDF
Lab1 Solution : Stimulus Modeling
Video
00:16:02
Lab2 Solution : Factory Overriding
Video
00:08:19
Lab3 Solution : UVM Phases
Video
00:10:22
Lab4 Solution : Creating UVM agent
Video
00:11:44
Lab5 Solution : UVM Sequences
Video
00:13:22
Lab6 Solution : Virtual Interface
Video
00:05:50
Lab7 Solution : Agent Integration
Video
00:08:12
Lab8 Solution : UVM Scoreboard
Video
00:06:39
Lab9 Solution : SoC - UVM VE implementation
Video
00:08:41
Lab10 Solution : Coverage & Regression
Video
00:04:33
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
00:15:55
UVM RAL - Adapter, Predictor and Integration
Video
00:20:36
UVM RAL - Definition of Register Sequences
Video
00:11:55
Knowledge Check - UVM RAL
Exercise
ARM Architecture
5 Learning Materials
ARM Architecture
ARM - Introduction to ARM
Video
00:10:23
ARM - ARM Architecture Versions and Profiles
Video
00:13:31
ARM - ARM Architecture Vs Micro Architecture
Video
00:06:25
ARM - ARM registers and Instructions
Video
00:12:49
ARM - Exceptions in ARM
Video
00:13:09
ARM Debug
ARM Software Interfaces and Programming
AMBA Protocols - AXI, AHB, APB
17 Learning Materials
Introduction to AMBA
Introduction to AMBA
Video
00:07:10
APB Protocol
APB - Signal Decritption
Video
00:04:28
APB - Data Transfers
Video
00:05:22
AHB Protocol
AHB - Write Read Transfers
Video
00:10:46
AHB - Signal Description
Video
00:07:56
AHB - Locked and Wait Transfers
Video
00:07:18
AHB - Slave Response
Video
00:04:55
AHB - Interconnect
Video
00:09:07
AXI Protocol
Introduction to AXI
Video
00:04:29
AXI - Channel Handshake
Video
00:03:57
AXI - Write and Read Transfers
Video
00:03:56
AXI - Channel Dependencies
Video
00:05:52
AXI - Signal Description
Video
00:08:30
AXI - Atomic Access
Video
00:10:35
AXI - Responses and Strobe Signals
Video
00:06:05
AXI - Transfer Ordering
Video
00:03:02
AXI - Interconnect
Video
00:05:51
SoC External Interfaces - SPI, UART, I2C, GPIO, JTAG
6 Learning Materials
GPIO
GPIO Protocol Specification
Video
00:17:18
SPI
SPI Protocol Specification
Video
00:14:07
UART
UART Protocol Specification
Video
00:26:47
JTAG
Intdroction to JTAG
Video
00:24:31
JTAG Protocol Specification
Video
00:19:05
I2C
I2C Protocol Specification
Video
00:26:23
Low Power Design
Low Power Verification
4 Learning Materials
Reference Material
Low Power Concepts
PDF
UPF Introduction
PDF
How to Write UPF
PDF
Project - Power Aware Verification
Power Aware Verification Project Specification
PDF
Gate Level Simulation [ GLS ]
1 Exercises • 7 Learning Materials
GLS
GLS Flow
PDF
GLS Introduction
Video
00:09:31
Feedback Form
External Link
SDF Simulation
Video
00:13:02
Test Plan for GLS
Video
00:06:57
GLS Demo
Video
00:10:14
GLS - Knowledge check
Exercise
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Embedded C Programming
13 Learning Materials
C Programming
C Programming - Basics of C Part 1
Video
01:09:13
C Programming - Basics of C Part 2
Video
00:56:39
C Programming - Basics of C Part 3
Video
00:17:27
C Programming - Control flow & Loops Part 1
Video
00:30:02
C Programming - Control flow and Loops Part 2
Video
00:56:52
C Programming - Strings
Video
00:32:21
C Programming - Pointers
Video
00:29:16
C Programming - Arrays
Video
00:48:37
C Programming- Pointers and Arrays
Video
00:24:02
C Programming - Functions
Video
00:59:14
C Programming- Structures and Unions
Video
01:01:43
C Programming - Linked lists
Video
00:58:47
C Programming - Accessing Registers
Video
00:57:20
Portable Stimulus Standard [ PSS ]
Python for DV Automation
Case Study : Microchip Polarfire SoC - RISC-V SoC on FPGA
1 Learning Materials
Case Study : Microchip Polarfire SoC
Case Study : Microchip Polarfile SoC
Video
00:40:27
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