VLSI Physical Design - Campus Connect
Join Maven Silicon's Blended VLSI Physical Design course to learn physical design intricacies with a balanced mix of theory and hands-on experience.
₹2999.00 ₹5000.00 40% OFF
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Course Overview
This course provides a comprehensive overview of key concepts in VLSI SoC Design and various techniques involved in the VLSI design flow. The course provides a comparison between ASIC and FPGA technologies and focuses on advanced digital design and Verilog HDL and also on various design styles, different techniques involved for partitioning, floor-planning, routing etc.. and also it gives an insights on various timing procedures and timing closure.
Schedule of Classes
Course Curriculum
8 Subjects
VLSI COE- M1 - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Smartphone - SoC - Architecture
SoC Design
ASIC Vs FPGA
Knowledge Check : Introduction to VLSI
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
ASIC Design Flow - Part-2 (Architecture to RTL Design)
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
ASIC Design Flow - Part-4 (DFT to STA)
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
VLSI COE- M2 - Advanced Digital Design
8 Exercises • 10 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Digital Design Reference Book - Downloadable
Digital Design Reference Book
Number System and Codes
Number Systems and Codes - Basics
Knowledge Check : Number Systems and Codes
Logic Circuits
Logic Circuits
Knowledge Check : Logic Circuits and Boolean Algebra-1
Combinational Circuits
Combinational Circuits - I
Knowledge Check : Combinational Circuits - I
Combinational Circuits - II
Knowledge Check : Combinational Circuits - 2
Sequential Circuits
Sequential Circuits - I
Knowledge Check : Sequential Circuits -1
Sequential Circuits - II
Knowledge Check : Sequential Circuits -2
Finite State Machine FSM
FSM
Knowledge Check : FSM
Memories
Memories
Knowledge Check :Memories -1
VLSI COE- M4- Verilog HDL
8 Exercises • 30 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Style
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Instructions - Verilog Labs
Verilog Lab Manual
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab1
Solution to Lab 2
Solution to Lab 3
Solution to Lab 4
Solution to Lab 5
Solution to Lab 6
RISC-V RTL Design
ALU Design
ALU Verification
Integer file design
Integer File Verification
RISC-V RTL Design & Verification Part -1
RISC-V RTL Design & Verification Part -2
RISC-V RTL Design & Verification Part -3
RISC-V RTL Design & Verification Part -4
VLSI COE- M6 - Static Timing Analysis
6 Exercises • 14 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
Knowledge Check - STA Introduction
STA Reference Book
STA Reference Book
STA: Clock
Clock - Part -1
Clock - Part - 2
Knowledge Check - Clock
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
Knowledge Check - Timing Parameters
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
Knowledge Check - Timing analysis Procedure
STA : Techniques to Improve Timing
Different Techniques to improve timing
Knowledge Check - Techniques to Improve Timing
Module Test : STA
Module Test : STA
VLSI COE- M11 - Physical Design
23 Learning Materials
Physical Design Processes - Overview
Intro to VLSI
Design Styles
Partitioning
Floor-planning
placement
CTS
Routing
Static Timing Analysis (STA)
Physical Verification
physical_verification
Design_Rules
calibre_drc_flow
How to solve DRC Using Calibre nmdrc tool
Layout Versus Schematic
calibre nmlvs flow
Project Demo: RISC-V Design Implementation Using DC + ICC Tools
RISC – V IP Physical Design Implementation Using DC and ICC2
RISC-V QRG
RISC-V Implementation Using DC ICCII Flow
Synthesis tcl script
Synthesis Using DC - Running Script and Viewing Schematic
Analysing area timing and Power reports
Design setup and Floorplanning
Power Planning
Placement_CTS_Routing
VLSI COE- M12 - Business Communication
5 Learning Materials
Business Communication Skills
Email Writing - Tips and Tricks
Unsaid rules of the workplace
Why and What of an Interview- All about the Mindset
Telephone and Video Etiquette
How to ace a job interview?
Digital Design - Hands On
18 Learning Materials
Digital Electronics
Introduction to Digital Electronics
Number Systems and Codes
Assignment 1
Solution to Assignment 1
Logic Circuits
Assignment 2
Solution to Assignment 2
Combinational Circuits
Assignment 3
Solution to Assignment 3
Assignment 4
Solution to Assignment 4
Sequential Circuits
Assignment 5
Solution to Assignment 5
Assignment 6
Solution to Assignment 6
Finite State Machines
Assignment 7
Solution to Assignment 7
Feedback Form
Feedback Form
Memories
Assignment 8
Solution to Assignment 8
Verilog HDL - Hands On
5 Learning Materials
Verilog HDL Review
Verilog HDL Summary
Verilog RTL Coding Examples
Feedback Form
Feedback Form
Verilog Project
Explanation to Project Specification
Alarm Clock Project Specification
Course Instructor
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