VLSI Verification - Campus Connect
Optimize your VLSI designs with effective verification at Maven Silicon. Explore the proven strategies and methodologies for robust VLSI verification processes.
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Course Overview
Welcome to the VLSI Verification course – your comprehensive journey into mastering verification methodologies in VLSI design. This course covers a range of modules, from the basics to in-depth discussions on Advanced Digital Design, Verilog HDL to SystemVerilog language concepts like memories, interfaces, object-oriented programming, randomization, functional coverage, SystemVerilog Assertions and more. Conclude with an overview of the Universal Verification Methodology. Join us on this insightful exploration into the world of VLSI Verification!
Schedule of Classes
Course Curriculum
10 Subjects
VLSI COE- M1 - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Smartphone - SoC - Architecture
SoC Design
ASIC Vs FPGA
Knowledge Check : Introduction to VLSI
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
ASIC Design Flow - Part-2 (Architecture to RTL Design)
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
ASIC Design Flow - Part-4 (DFT to STA)
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
VLSI COE- M2 - Advanced Digital Design
8 Exercises • 10 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Digital Design Reference Book - Downloadable
Digital Design Reference Book
Number System and Codes
Number Systems and Codes - Basics
Knowledge Check : Number Systems and Codes
Logic Circuits
Logic Circuits
Knowledge Check : Logic Circuits and Boolean Algebra-1
Combinational Circuits
Combinational Circuits - I
Knowledge Check : Combinational Circuits - I
Combinational Circuits - II
Knowledge Check : Combinational Circuits - 2
Sequential Circuits
Sequential Circuits - I
Knowledge Check : Sequential Circuits -1
Sequential Circuits - II
Knowledge Check : Sequential Circuits -2
Finite State Machine FSM
FSM
Knowledge Check : FSM
Memories
Memories
Knowledge Check :Memories -1
VLSI COE- M4- Verilog HDL
8 Exercises • 30 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Style
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Instructions - Verilog Labs
Verilog Lab Manual
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab1
Solution to Lab 2
Solution to Lab 3
Solution to Lab 4
Solution to Lab 5
Solution to Lab 6
RISC-V RTL Design
ALU Design
ALU Verification
Integer file design
Integer File Verification
RISC-V RTL Design & Verification Part -1
RISC-V RTL Design & Verification Part -2
RISC-V RTL Design & Verification Part -3
RISC-V RTL Design & Verification Part -4
VLSI COE- M6 - Static Timing Analysis
6 Exercises • 14 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
Knowledge Check - STA Introduction
STA Reference Book
STA Reference Book
STA: Clock
Clock - Part -1
Clock - Part - 2
Knowledge Check - Clock
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
Knowledge Check - Timing Parameters
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
Knowledge Check - Timing analysis Procedure
STA : Techniques to Improve Timing
Different Techniques to improve timing
Knowledge Check - Techniques to Improve Timing
Module Test : STA
Module Test : STA
VLSI COE- M7 - System Verilog HDVL
2 Exercises • 14 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Constraint Random Coverage Driven Verification
Verification Methodologies & Summary
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Transactions
SV Interface
SV Virtual Interface
SV OOP
SV Randomization & Functional Coverage
SV TB Architecture
Knowledge Check : SV language Concepts Overview
VLSI COE- M8 - System Verilog Assertions
1 Exercises • 3 Learning Materials
SVA Introduction & Types of Assertions
What are Assertions?
Necessity of using SystemVerilog Assertions
Types of Assertions
SVA - Knowledge Check - 1
VLSI COE- M9 - Universal Verification Methodology
1 Exercises • 3 Learning Materials
Universal Verification Methodology Overview
UVM_Introduction
Advanced_UVM_CaseStudies
Knowledge Check : Introduction to UVM
RISC-V Verification using UVM - Demo
RISC-V Verification using UVM - Demo
VLSI COE- M12 - Business Communication
5 Learning Materials
Business Communication Skills
Email Writing - Tips and Tricks
Unsaid rules of the workplace
Why and What of an Interview- All about the Mindset
Telephone and Video Etiquette
How to ace a job interview?
Digital Design - Hands On
18 Learning Materials
Digital Electronics
Introduction to Digital Electronics
Number Systems and Codes
Assignment 1
Solution to Assignment 1
Logic Circuits
Assignment 2
Solution to Assignment 2
Combinational Circuits
Assignment 3
Solution to Assignment 3
Assignment 4
Solution to Assignment 4
Sequential Circuits
Assignment 5
Solution to Assignment 5
Assignment 6
Solution to Assignment 6
Finite State Machines
Assignment 7
Solution to Assignment 7
Feedback Form
Feedback Form
Memories
Assignment 8
Solution to Assignment 8
Verilog HDL - Hands On
5 Learning Materials
Verilog HDL Review
Verilog HDL Summary
Verilog RTL Coding Examples
Feedback Form
Feedback Form
Verilog Project
Explanation to Project Specification
Alarm Clock Project Specification
Course Instructor
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