Executive MTech in VLSI Design
Delve into the training of RISC-V powered SoC Design and Verification through the Executive MTech in VLSI Design program
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Course Overview
The course Executive M.Tech in VLSI Design is a postgraduate program designed for working professionals looking to enhance their expertise in VLSI Design without a career break. The course is offered as a hybrid, blended learning approach, combining online and in-person (weekend) classroom sessions. It is a RISC-V powered program that typically covers core VLSI concepts, advanced design techniques, and specialized areas like AI accelerators for VLSI along with practical hands-on experience using EDA tools.
Course Curriculum
6 Subjects
Executive MTech - Refresher Module
29 Exercises • 97 Learning Materials
Curriculum
Curriculum
PDF
Academic Calendar Cohort 1 Sem1
PDF
Semiconductor Industry
Why Semiconductors?
Video
00:10:53
Semiconductor Supply CHain
Video
00:12:31
Semiconductor Ecosystem
Video
00:13:34
AI-Driven
Video
00:07:21
Knowledge Check - Semiconductor Industry
Exercise
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
00:13:26
Number System and Codes
Number Systems and Codes - Basics
Video
00:37:45
Knowledge Check : Number systems-1
Exercise
Number Systems
Video
00:27:09
Codes
Video
00:10:09
Knowledge Check : Number system and Codes-2
Exercise
Logic Circuits
Logic Circuits
Video
00:55:07
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
00:50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Combinational Circuits - Basics
Combinational Circuits - I
Video
00:28:25
Knowledge check : Combinational Circuits Basics-1
Exercise
Combinational Circuits - II
Video
00:44:08
Knowledge Check : Combinational Circuits Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
00:21:08
Combinational Logic Circuits - Delays
Video
00:09:11
Encoders, decoders and Magnitude Comparators
Video
00:11:41
Knowledge Check : Combinational Circuits Advanced-1
Exercise
Multiplexers and Demultiplexers
Video
00:18:58
Universal Logic Gates and Tristate Buffers
Video
00:08:37
Summary & Knowledge Check
Video
00:25:42
Knowledge Check : Combinational Circuits Advanced -2
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
00:40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
00:45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
00:25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
00:13:16
Knowledge Check : Sequential Circuits Advanced -1
Exercise
Registers & Counters
Video
00:37:19
Sequence Generators & Frequency dividers
Video
00:26:02
Knowledge Check : Sequential Circuits Advanced -2
Exercise
Finite State Machine - Basics
FSM
Video
00:37:39
Knowledge Check : FSM
Exercise
Finite State Machine - Advanced
Finite State Machines - Part - 1
Video
00:27:44
Finite State Machines - Part - 2
Video
00:21:43
Knowledge Check : Finite State Machines
Exercise
Memories
Memories
Video
00:25:54
Knowledge Check Memories -1
Exercise
Memories & PLD
Video
00:29:45
Knowledge Check : Memories, Glitches and PLD)
Exercise
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
RTL Coding Guidelines
RTL Coding Guidelines
PDF
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
Verilog Labs
ZIP
Instructions - Verilog Labs
PDF
EDA Tools - Installation Guide
Video
00:18:50
VirtualBox_Ubuntu_Installation_on_windows
PDF
Xilinx ISE Installation Guide
PDF
Xilinx_Installation_video
Video
00:20:16
Verilog Lab Manual - Xilinx ISE
PDF
EDA Tools - User Guide
Video
00:05:22
Must read Instruction manual
PDF
Verilog Lab Manual - Modelsim and DC
PDF
Verilog_lab_manual_modelsim_quartus
PDF
Advanced Verilog
Timescale system task & localparm
Video
00:14:48
Generate block & Continuous Procedural Assignments
Video
00:18:37
Feedback Form
External Link
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
00:15:34
Named Events and Stratified Event Queue
Video
00:19:56
Knowledge Check- Advance Verilog 2
Exercise
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Feedback Form
External Link
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Knowledge Check-Code Coverage 1
Exercise
Router 1x3 RTL Design
Router_1x3_design - Specification
PDF
Introduction to Router
Video
00:10:53
Router Top Packet Structure
Video
00:07:16
Input Output Protocol
Video
00:04:40
Router Architecture
Video
00:19:17
Router Design Solution Videos
Router_fifo
Video
00:20:58
Router_synchronizer
Video
00:14:06
Router_fsm
Video
00:17:17
Router_register
Video
00:20:58
Router_top
Video
00:19:04
RTL Synthesis and Lint
RTL Synthesis - Part-1
Video
00:17:26
RTL Synthesis - Part-2
Video
00:06:16
DC - Ultra
Video
00:02:23
VC Spyglass - Lint
Video
00:31:17
VC_Spyglass_Lint
PDF
Executive MTech - System on Chip Design
93 Learning Materials
Introduction to System on Chip & Basics of Chip Design
Microcontrollers Vs Complex SoCs
Video
00:23:06
Computer System Architecture - Von Neuman Vs Harvard
Video
00:21:52
SoC Design Considerations and RISC-V ISA Overview
Video
00:22:02
RISC-V Toolchain, CPU, and Memories - Physical Vs Virtual
Video
00:15:08
MMUs and Interrupt Controllers
Video
00:17:50
SoC Design - PPA, SoC Manufacturing and Packaging
Video
00:13:41
Boot Flow
PDF
Interconnect & System Controller
Advanced Peripheral Bus : Introduction
Video
00:00:15
Introduction to SoC : APB
Video
00:00:00
Advanced Peripheral Bus : Agenda & Objective
Video
00:00:00
Advanced Peripheral bus : Operations
Video
00:00:00
APB & AHB : A Comparission
Video
00:00:00
Advanced Peripheral bus : Summary
Video
00:00:00
Advanced High-Performance Bus : Introduction
Video
00:00:00
Introduction to SoC : AHB
Video
00:00:00
Advanced High-Performance Bus : Agenda & Objective
Video
00:00:00
Advanced High-Performance Bus : Features
Video
00:00:00
Advanced High-Performance Bus : Operations
Video
00:00:00
Advanced High-Performance Bus : Basic Transfers
Video
00:00:00
Advanced High-Performance Bus : Signal Description
Video
00:00:00
Advanced High-Performance Bus : Protection Support
Video
00:00:00
Advanced High-Performance Bus : Slave Responses
Video
00:00:00
Advanced High-Performance Bus : Interconnects
Video
00:00:00
AHB and AXI : A Comparission
Video
00:00:00
Advanced High-Performance Bus : Summary
Video
00:00:00
Advanced eXtensible Bus : Introduction
Video
00:00:00
Advanced eXtensible Bus : Features
Video
00:00:00
Advanced eXtensible Bus : Transfers
Video
00:00:00
Advanced eXtensible Bus : Channel Dependancies
Video
00:00:00
Advanced eXtensible Bus : Signal Description
Video
00:00:00
Advanced eXtensible Bus : Protection & Cache Support
Video
00:00:00
Advanced eXtensible Bus : Atomic Access
Video
00:00:00
Advanced eXtensible Bus : Other Features
Video
00:00:00
Advanced eXtensible Bus : Interconnects
Video
00:00:00
Advanced eXtensible Bus : Summary
Video
00:00:00
Memory and Cache
Introduction to Memories
Video
00:05:07
Volatile Memories
Video
00:27:32
Non-Volatile Memories
Video
00:12:24
Memory Controllers
Video
00:11:01
Interfacing with External World
I2C Introduction
Video
00:04:32
I2C_Topology
Video
00:05:09
I2C Data Transfer
Video
00:13:48
I2C Arbitration & Clock Stretching
Video
00:08:02
I2C Physical Layer
Video
00:02:40
I2C Implementation
Video
00:06:52
I2C Case Study
Video
00:02:18
Introduction to SPI
Video
00:06:15
SPI Architetcure
Video
00:13:11
SPI Multiple Slaves Configuration
Video
00:03:20
SPI Example Implementation
Video
00:07:30
SPI Case Study
Video
00:04:08
Introduction to UART
Video
00:05:56
UART Architetcure
Video
00:24:23
UART Example Implementation
Video
00:15:49
UART Case Study
Video
00:02:13
Introduction to PCIe
Video
00:11:10
PCIe Normal vs Differential Signalling
Video
00:06:05
PCIe Overview
Video
00:11:40
Introduction to USB
Video
00:19:44
USB Device Architecture
Video
00:08:59
USB Functional layer
Video
00:28:26
SoC Design Labs
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
RISC-V Core Design by Integrating the Subblocks & verifying the core using Encrypted UVM Testbench
Video
00:38:50
Lab Manual
PDF
Refrence Material
SoC Overview
PDF
RISCV SoC
PDF
SoC Address Map
PDF
SoC Design Requirements
PDF
AXI
PDF
AHB
PDF
APB
PDF
System Controller
PDF
Memories and Memory Controllers
PDF
Peripheral Protocols - General
PDF
UART
PDF
SPI
PDF
I2C
PDF
Ethernet_WiFi
PDF
GPIO
PDF
USB
PDF
Software for SoC
PDF
ISA-I QP
PDF
Practice Questions
PDF
Peripheral Protocols - General
Executive MTech - Advanced Computer Architecture
1 Exercises • 73 Learning Materials
General Computer Architecture and Memory Organization
General Computer Architecture
PDF
General Computer Architecture and Memory Organization-1
Video
01:00:08
General Computer Architecture and Memory Organization-2
Video
01:09:50
General Computer Architecture and Memory Organization-3
Video
01:06:29
General Computer Architecture and Memory Organization-4
Video
01:44:02
Cache Architecture
Memory Hierarchy
Video
00:03:40
Cache Introduction
Video
00:06:13
Cache Associativity
Video
00:07:09
Cache Policies
Video
00:04:19
Cache Coherency
Video
00:14:58
RISC-V
RISC-V Overview
Video
00:09:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
Video
00:15:16
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
Video
00:17:12
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
Video
00:14:57
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
Video
00:06:10
RISC-V M Extensions
Video
00:09:13
RISC-V A Extension
Video
00:16:28
RISC-V C-Extension - Part-1 (Introduction to C Extension)
Video
00:12:07
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Video
00:08:47
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Video
00:15:04
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
Video
00:13:39
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Video
00:15:34
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Video
00:22:36
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Video
00:16:29
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
Video
00:09:45
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Video
00:14:57
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Video
00:15:48
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Video
00:21:12
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Video
00:19:09
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Video
00:03:34
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Video
00:11:01
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Video
00:12:20
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Video
00:07:45
Hypervisor - Part-4 (VS Mode CSR's)
Video
00:07:58
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Video
00:05:34
RISC-V PMA and PMP
Video
00:18:04
RISC-V OS - Overview
Video
00:09:29
RISC-V OS - Booting Process
Video
00:17:03
RISC-V OS - Paging
Video
00:18:27
RISC-V OS - Kernel Traps
Video
00:14:24
RISC-V OS - User Traps
Video
00:18:55
ABI_V1(Introduction to ABI)
Video
00:06:54
ABI_V2 (RISC-V Calling Conventions Part-1)
Video
00:32:44
ABI_V3 (RISC-V Calling Conventions Part-2)
Video
00:12:09
ABI_V4 (RISC-V Calling Conventions Part-3)
Video
00:14:45
ABI_V5 (RISC_V ELF Specifications)
Video
00:41:30
ABI_V6 (RISC-V Linker Relaxation)
Video
00:06:09
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
Video
00:34:12
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Video
00:33:33
Submit your RISC-V Assignment here
Assignment
ARM
ARMv8A Architecture
PDF
Refernce Material
RISC-V Overview
PDF
RISC-V Base ISA
PDF
RV32I Instructions
PDF
RV32A Instructions
PDF
RV32 F&D Instructions
PDF
RV32M instructions
PDF
RV32 Compressed Instructions
PDF
Machine ISA
PDF
Supervisor ISA
PDF
RISC-V Assembly
PDF
RISC-v Tool Chain
PDF
RISC-V Debug
PDF
RISC-V PLIC
PDF
Xv6 _OS_casestudy
PDF
Cache Architecture
PDF
ARM v8A Architecture
PDF
ISA-I QP
PDF
Practice Questions
PDF
Executive MTech - Analog Mixed Signal Design
1 Exercises • 23 Learning Materials
Analog Refresher
Analog Basics
PDF
Analog Refresher
PDF
AMS Assignment -1
Assignment
Analog Circuit Functions and Applications -1
Video
01:10:51
Analog Circuit Functions and Applications -2
Video
00:55:12
Analog Sub-systems I
Analog Sub-SystemsI
PDF
Analog Sub-Systems II
Analog SubSytems-II
PDF
AMS Behavioural Modelling
Verilog AMS
PDF
AMS Labs
Lab Manual
PDF
Lab1
Video
00:13:47
Lab2
Video
00:16:38
Lab3
Video
00:17:02
Lab4
Video
00:14:31
Lab5
Video
00:09:13
Verilog AMS Lab Introduction
Video
00:02:20
Lab6
Video
00:30:05
Lab7
Video
00:21:38
Lab8
Video
00:13:02
Lab9
Video
00:19:03
Lab10
Video
00:10:40
Refernce Material
ISA-I QP
PDF
Practice Problems
PDF
AMS Assignment
Assignment 1,2,3
PDF
ISA-I QP
PDF
Synopsys VCS and Verdi - Tool Demos
1 Exercises • 6 Learning Materials
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
00:10:14
Verdi Tool Demo - Part-1
Video
00:09:16
Verdi Tool Demo - Part-2
Video
00:07:48
Verdi Tool Demo - Part- 3
Video
00:18:04
Feedback Form
External Link
Verdi Debugging - Knowledge Check
Exercise
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Executive MTech - Development of RISC -V based SoC RTL
2 Learning Materials
Project Specification
Project Specification
Video
01:14:46
Reference Material
PDF
Course Instructor
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