Executive MTech in VLSI Design
Delve into the training of RISC-V powered SoC Design and Verification through the Executive MTech in VLSI Design program
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Course Overview
The course Executive M.Tech in VLSI Design is a postgraduate program designed for working professionals looking to enhance their expertise in VLSI Design without a career break. The course is offered as a hybrid, blended learning approach, combining online and in-person (weekend) classroom sessions. It is a RISC-V powered program that typically covers core VLSI concepts, advanced design techniques, and specialized areas like AI accelerators for VLSI along with practical hands-on experience using EDA tools.
Course Curriculum
12 Subjects
Executive MTech - Refresher Module
29 Exercises • 100 Learning Materials
Curriculum
Curriculum
PDF
Academic Calendar Cohort 1 Sem1
PDF
Academic Calendar Cohort2 Sem1
PDF
ExecutiveMTech Program Calendar of Events Cohort1 Sem2
PDF
Academic Calendar Cohort 3 Sem1
PDF
Semiconductor Industry
Why Semiconductors?
Video
00:10:53
Semiconductor Supply CHain
Video
00:12:32
Semiconductor Ecosystem
Video
00:13:34
AI-Driven
Video
00:07:22
Knowledge Check - Semiconductor Industry
Exercise
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:44
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:08
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:06
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
00:13:26
Number System and Codes
Number Systems and Codes - Basics
Video
00:37:45
Knowledge Check : Number systems-1
Exercise
Number Systems
Video
00:27:09
Codes
Video
00:10:09
Knowledge Check : Number system and Codes-2
Exercise
Logic Circuits
Logic Circuits
Video
00:55:07
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
00:50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Combinational Circuits - Basics
Combinational Circuits - I
Video
00:28:25
Knowledge check : Combinational Circuits Basics-1
Exercise
Combinational Circuits - II
Video
00:44:08
Knowledge Check : Combinational Circuits Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
00:21:08
Combinational Logic Circuits - Delays
Video
00:09:11
Encoders, decoders and Magnitude Comparators
Video
00:11:41
Knowledge Check : Combinational Circuits Advanced-1
Exercise
Multiplexers and Demultiplexers
Video
00:18:58
Universal Logic Gates and Tristate Buffers
Video
00:08:37
Summary & Knowledge Check
Video
00:25:42
Knowledge Check : Combinational Circuits Advanced -2
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
00:40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
00:45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
00:25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
00:13:16
Knowledge Check : Sequential Circuits Advanced -1
Exercise
Registers & Counters
Video
00:37:19
Sequence Generators & Frequency dividers
Video
00:26:02
Knowledge Check : Sequential Circuits Advanced -2
Exercise
Finite State Machine - Basics
FSM
Video
00:37:39
Knowledge Check : FSM
Exercise
Finite State Machine - Advanced
Finite State Machines - Part - 1
Video
00:27:44
Finite State Machines - Part - 2
Video
00:21:43
Knowledge Check : Finite State Machines
Exercise
Memories
Memories
Video
00:25:54
Knowledge Check Memories -1
Exercise
Memories & PLD
Video
00:29:45
Knowledge Check : Memories, Glitches and PLD)
Exercise
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
RTL Coding Guidelines
RTL Coding Guidelines
PDF
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
Verilog Labs
ZIP
Instructions - Verilog Labs
PDF
EDA Tools - Installation Guide
Video
00:18:50
VirtualBox_Ubuntu_Installation_on_windows
PDF
Xilinx ISE Installation Guide
PDF
Xilinx_Installation_video
Video
00:20:17
Verilog Lab Manual - Xilinx ISE
PDF
EDA Tools - User Guide
Video
00:05:22
Must read Instruction manual
PDF
Verilog Lab Manual - Modelsim and DC
PDF
Verilog_lab_manual_modelsim_quartus
PDF
Advanced Verilog
Timescale system task & localparm
Video
00:14:48
Generate block & Continuous Procedural Assignments
Video
00:18:37
Feedback Form
External Link
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
00:15:34
Named Events and Stratified Event Queue
Video
00:19:56
Knowledge Check- Advance Verilog 2
Exercise
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Feedback Form
External Link
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Knowledge Check-Code Coverage 1
Exercise
Router 1x3 RTL Design
Router_1x3_design - Specification
PDF
Introduction to Router
Video
00:10:53
Router Top Packet Structure
Video
00:07:16
Input Output Protocol
Video
00:04:40
Router Architecture
Video
00:19:17
Router Design Solution Videos
Router_fifo
Video
00:20:58
Router_synchronizer
Video
00:14:06
Router_fsm
Video
00:17:17
Router_register
Video
00:20:58
Router_top
Video
00:19:04
RTL Synthesis and Lint
RTL Synthesis - Part-1
Video
00:17:26
RTL Synthesis - Part-2
Video
00:06:16
DC - Ultra
Video
00:02:23
VC Spyglass - Lint
Video
00:31:17
VC_Spyglass_Lint
PDF
Executive MTech - System on Chip Design
106 Learning Materials
Feedback form - SOC
Feeback form - SOC
feedback_form
Microcontrollers and SoC architecture
Microcontrollers Vs Complex SoCs
Video
00:23:07
Computer System Architecture - Von Neuman Vs Harvard
Video
00:21:52
SoC Design Considerations and RISC-V ISA Overview
Video
00:22:02
RISC-V Toolchain, CPU, and Memories - Physical Vs Virtual
Video
00:15:08
MMUs and Interrupt Controllers
Video
00:17:51
SoC Design - PPA, SoC Manufacturing and Packaging
Video
00:13:41
Boot Flow
PDF
Interconnect & System Controller
Advanced Peripheral Bus : Introduction
Video
00:00:16
Introduction to SoC : APB
Video
00:08:59
Advanced Peripheral Bus : Agenda & Objective
Video
00:04:03
Advanced Peripheral bus : Operations
Video
00:06:24
APB & AHB : A Comparission
Video
00:01:07
Advanced Peripheral bus : Summary
Video
00:00:28
Advanced High-Performance Bus : Introduction
Video
00:00:31
Introduction to SoC : AHB
Video
00:08:58
Advanced High-Performance Bus : Agenda & Objective
Video
00:00:50
Advanced High-Performance Bus : Features
Video
00:02:59
Advanced High-Performance Bus : Operations
Video
00:01:25
Advanced High-Performance Bus : Basic Transfers
Video
00:05:12
Advanced High-Performance Bus : Signal Description
Video
00:18:28
Advanced High-Performance Bus : Protection Support
Video
00:00:52
Advanced High-Performance Bus : Slave Responses
Video
00:05:40
Advanced High-Performance Bus : Interconnects
Video
00:10:23
AHB and AXI : A Comparission
Video
00:02:17
Advanced High-Performance Bus : Summary
Video
00:00:54
Advanced eXtensible Bus : Introduction
Video
00:09:12
Advanced eXtensible Bus : Features
Video
00:10:46
Advanced eXtensible Bus : Transfers
Video
00:04:51
Advanced eXtensible Bus : Channel Dependancies
Video
00:05:14
Advanced eXtensible Bus : Signal Description
Video
00:07:08
Advanced eXtensible Bus : Protection & Cache Support
Video
00:05:39
Advanced eXtensible Bus : Atomic Access
Video
00:11:16
Advanced eXtensible Bus : Other Features
Video
00:17:47
Advanced eXtensible Bus : Interconnects
Video
00:05:43
Advanced eXtensible Bus : Summary
Video
00:03:54
Memory and Cache
Introduction to Memories
Video
00:05:08
Volatile Memories
Video
00:27:33
Non-Volatile Memories
Video
00:12:25
Memory Controllers
Video
00:11:01
Interfacing with External World
I2C Introduction
Video
00:04:33
I2C_Topology
Video
00:05:09
I2C Data Transfer
Video
00:13:48
I2C Arbitration & Clock Stretching
Video
00:08:02
I2C Physical Layer
Video
00:02:41
I2C Implementation
Video
00:06:52
I2C Case Study
Video
00:02:18
Introduction to SPI
Video
00:06:16
SPI Architetcure
Video
00:13:12
SPI Multiple Slaves Configuration
Video
00:03:20
SPI Example Implementation
Video
00:07:31
SPI Case Study
Video
00:04:09
Introduction to UART
Video
00:05:57
UART Architetcure
Video
00:24:24
UART Example Implementation
Video
00:15:49
UART Case Study
Video
00:02:14
Introduction to PCIe
Video
00:11:11
PCIe Normal vs Differential Signalling
Video
00:06:05
PCIe Overview
Video
00:11:40
Introduction to USB
Video
00:19:45
USB Device Architecture
Video
00:09:00
USB Functional layer
Video
00:28:26
Refrence Material
SoC Overview - Part 1
PDF
RISCV SoC - Part 2
PDF
SoC Address Map
PDF
SoC Design Requirements : Part 3
PDF
AXI
PDF
AHB
PDF
APB
PDF
System Controller
PDF
Memories and Memory Controllers
PDF
Peripheral Protocols - General
PDF
UART
PDF
SPI
PDF
I2C
PDF
Ethernet_WiFi
PDF
GPIO
PDF
USB
PDF
Software for SoC
PDF
ISA-I QP
PDF
ISA-II QP
PDF
Practice Questions
PDF
SoC Design - ESA Practice Questions
PDF
Practice Questions
PDF
Practice Questions 2
PDF
ESA - Practice Questions SOC
PDF
ISA 2 - SOC QP with Solutions
PDF
ISA 1 - QP with Solutions
PDF
Peripheral Protocols - General
SoC Design Labs
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
Lab Manual
PDF
SoC Design -ALU(Lab01& Lab02)
Video
01:57:26
SoC Design - Integer File(Lab03&4)
Video
01:55:08
SoC Design- CSR block(Lab05)
Video
01:32:46
SoC Design - CSR Block TB(Lab06)
Video
01:31:32
SoC Design - Machine Control Unit(Lab07&08)
Video
01:45:26
RISC-V Core Design by Integrating the Subblocks & verifying the core using Encrypted UVM Testbench(
Video
00:38:50
Executive MTech - Advanced Computer Architecture
1 Exercises • 82 Learning Materials
Feedback form - ACA
Feeback form - ACA
feedback_form
General Computer Architecture and Memory Organization
General Computer Architecture
PDF
General Computer Architecture and Memory Organization-1
Video
01:00:08
General Computer Architecture and Memory Organization-2
Video
01:09:50
General Computer Architecture and Memory Organization-3
Video
01:06:30
General Computer Architecture and Memory Organization-4
Video
01:44:03
General Compuer Architecture and Memory Organisation-5
Video
01:31:57
General Compuer Architecture and Memory Organisation-6
Video
01:25:11
Cache Architecture
Memory Hierarchy
Video
00:03:40
Cache Introduction
Video
00:06:13
Cache Associativity
Video
00:07:10
Cache Policies
Video
00:04:19
Cache Coherency
Video
00:14:58
RISC-V
RISC-V Overview
Video
00:09:43
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:10
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:20
RV32I Base Instructions (U type)
Video
00:17:12
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
Video
00:15:17
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
Video
00:17:12
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
Video
00:14:57
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
Video
00:06:11
RISC-V M Extensions
Video
00:09:13
RISC-V A Extension
Video
00:16:28
RISC-V C-Extension - Part-1 (Introduction to C Extension)
Video
00:12:07
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Video
00:08:47
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Video
00:15:05
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
Video
00:13:39
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Video
00:15:34
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Video
00:22:37
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Video
00:16:29
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
Video
00:09:46
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Video
00:14:57
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Video
00:15:48
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Video
00:21:12
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Video
00:19:10
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Video
00:03:35
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Video
00:11:02
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Video
00:12:20
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Video
00:07:45
Hypervisor - Part-4 (VS Mode CSR's)
Video
00:07:59
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Video
00:05:35
RISC-V PMA and PMP
Video
00:18:04
RISC-V OS - Overview
Video
00:09:30
RISC-V OS - Booting Process
Video
00:17:03
RISC-V OS - Paging
Video
00:18:27
RISC-V OS - Kernel Traps
Video
00:14:25
RISC-V OS - User Traps
Video
00:18:55
ABI_V1(Introduction to ABI)
Video
00:06:55
ABI_V2 (RISC-V Calling Conventions Part-1)
Video
00:32:44
ABI_V3 (RISC-V Calling Conventions Part-2)
Video
00:12:09
ABI_V4 (RISC-V Calling Conventions Part-3)
Video
00:14:46
ABI_V5 (RISC_V ELF Specifications)
Video
00:41:31
ABI_V6 (RISC-V Linker Relaxation)
Video
00:06:10
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
Video
00:34:12
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Video
00:33:33
Submit your RISC-V Assignment here
Assignment
Assignment
PDF
ARM
ARMv8A Architecture
PDF
Refernce Material
RISC-V Overview
PDF
RISC-V Base ISA
PDF
RV32I Instructions
PDF
RV32A Instructions
PDF
RV32 F&D Instructions
PDF
RV32M instructions
PDF
RV32 Compressed Instructions
PDF
Machine ISA
PDF
Supervisor ISA
PDF
RISC-V Assembly
PDF
RISC-v Tool Chain
PDF
RISC-V Debug
PDF
RISC-V PLIC
PDF
Xv6 _OS_casestudy
PDF
Cache Architecture
PDF
ARM v8A Architecture
PDF
Practice Questions
PDF
ARM Sample Questions
PDF
ISA-I QP
PDF
ISA-2
PDF
Practice Questions - ESA
PDF
ISA 2 - ACA QP with Solutions
PDF
ISA 1 - QP with Solutions
PDF
Executive MTech - Analog Mixed Signal Design
1 Exercises • 35 Learning Materials
Feedback form - AMS
Feeback form - AMS
feedback_form
Solved Question - Analog Refresher Unit 1
PDF
Analog Refresher
Analog Basics
PDF
Analog Refresher
PDF
AMS Assignment -1
Assignment
Analog Circuit Functions and Applications -1
Video
01:10:51
Analog Circuit Functions and Applications -2
Video
00:55:13
Practice Questions
PDF
Practice Questions 2
PDF
AMS Practice Questions - Unit 2
PDF
Analog Sub-systems I
Analog Sub-SystemsI
PDF
Analog Sub-Systems II
Analog SubSytems-II
PDF
AMS Behavioural Modelling
Verilog AMS
PDF
AMS Labs
Lab Manual
PDF
Lab1
Video
00:13:48
Lab2
Video
00:16:38
Lab3
Video
00:17:02
Lab4
Video
00:14:32
Lab5
Video
00:09:13
Verilog AMS Lab Introduction
Video
00:02:21
Lab6
Video
00:30:06
Lab7
Video
00:21:38
Lab8
Video
00:13:03
Lab9
Video
00:19:03
Lab10
Video
00:10:40
Refernce Material
ISA-I QP
PDF
ISA-II QP
PDF
Practice Problems
PDF
Practice Problems for ESA
PDF
Practice Solved Questions- ADC and DAC - Part 2
PDF
Practice Questions Analog Subsystems I & II (BGR, Regulator, Filter, Oscillator)
PDF
ISA 2 - AMS QP with Solutions
PDF
ISA 1 - QP with Solutions
PDF
AMS Assignment
Assignment 1,2,3
PDF
ISA-I QP
PDF
Cohort 2- AMS Assignment
PDF
Synopsys VCS and Verdi - Tool Demos
1 Exercises • 6 Learning Materials
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
00:10:14
Verdi Tool Demo - Part-1
Video
00:09:16
Verdi Tool Demo - Part-2
Video
00:07:48
Feedback form
feedback_form
Verdi Tool Demo - Part- 3
Video
00:18:05
Verdi Debugging - Knowledge Check
Exercise
Feedback Form - Overall Experience
Feedback form
feedback_form
Executive MTech - Development of RISC -V based SoC RTL
2 Learning Materials
Project Specification
Project Specification
Video
01:14:47
Reference Material
PDF
Executive MTech - Design For Testability for SoC's
66 Learning Materials
DFT Overview
Introduction to Testing and DFT
Video
00:12:51
Faults and Types of Testing
Video
00:07:40
Verification vs Testing
Video
00:03:12
Levels of Testing
Video
00:05:52
Fault Modelling
Video
00:11:38
TCL
Introduction to Tcl-1
PDF
Introduction to TCL-2
PDF
Introduction to Tcl
Video
00:15:29
Control Flow Statements
Video
00:26:26
Procedures
Video
00:17:05
Data types - Strings
Video
00:15:16
Mathematical Operators
Video
00:14:00
Datatypes - Lists
Video
00:19:45
Data types - Arrays
Video
00:11:38
Data types - Dictionaries
Video
00:10:23
Practice Applications
Video
00:11:47
TCL
Video
00:05:45
Tcl manual
PDF
Faults Modelling and ATPG
Fault Collapsing Part-1
Video
00:07:23
Fault Collapsing Part-2
Video
00:05:20
Fault Collapsing Part-3
Video
00:05:24
Combinational ATPG
Video
00:05:20
Introduction to ATPG
Video
00:04:56
D-Algorithm
Video
00:07:13
Fault Classes
Video
00:14:45
Additional Fault Models part-1
Video
00:11:46
Fault Simulation
Video
00:10:34
Additional Fault Models part-2
Video
00:08:02
DFT Implementation
Scan Insertion Part - 1
Video
00:07:17
Scan Insertion Part - 2
Video
00:03:04
Scan Insertion Part - 3
Video
00:04:44
Scan Insertion Part - 4
Video
00:05:38
Hierachical DFT Flow
Video
00:07:25
Test Compression
Video
00:14:51
Boundary Scan
Video
00:33:00
Introduction to BIST, LBIST & MBIST
Video
00:19:59
JTAG vs IJTAG
Video
00:10:05
Design Rule Checks
Video
00:03:04
Fault Diagnosis
Video
00:02:45
How to improve Test Coverage
Video
00:04:21
DFT Labs
Intro to Tessent
Video
00:03:37
System Modes
Video
00:03:13
TSDB Overview
Video
00:05:23
Solution to Lab 01
Video
00:10:32
Solution to Lab 02
Video
00:04:56
Solution to Lab 03
Video
00:05:12
Solution to Lab 04
Video
00:04:20
Solution to Lab 05
Video
00:02:22
Solution to Lab 06
Video
00:07:15
Solution to Lab 07
Video
00:06:49
Solution to Lab 08
Video
00:04:02
Solution to Lab 09
Video
00:08:23
Solution to Lab 11
Video
00:05:23
Solution to Lab 10
Video
00:05:29
Solution to Lab 12
Video
00:03:04
Solution to Lab 13
Video
00:09:57
Solution to Lab 14
Video
00:12:30
Solution to Lab 15
Video
00:07:25
Lab Manual
PDF
Feedback form
Feeback form - MTech DFT
feedback_form
Reference Material
DFT Material
PDF
ISA 1 - QP with Solutions (DFT)
PDF
DFT Assignments
PDF
Submit the DFT assignment in the G-form
External Link
ISA 2 QP - DFT
PDF
DFT Practice Questions
PDF
Executive MTech - SoC Verification using SystemVerilog & SVA
18 Exercises • 76 Learning Materials
Feedback form
Feeback form - MTech SV
feedback_form
Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Verification Methodologies & Summary
Video
00:27:11
Constraint Random Coverage Driven Verification
Video
00:25:37
Knowledge Check : Verification Methodology Overview
Exercise
SystemVerilog Language Concepts
SV Concepts Agenda
Video
00:06:38
SV Overview
Video
00:11:16
SV Randomization & Functional Coverage
Video
00:06:47
SV TB Architecture
Video
00:10:19
SV Interface
Video
00:14:51
SV Virtual Interface
Video
00:11:40
SV OOP
Video
00:13:56
SV Transactions
Video
00:14:46
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Introduction
SystemVerilog Introduction & Logic Data Type
Video
00:10:50
SV Data Types - 2 State, Struct & Enum
Video
00:15:27
SV Data Types - Strings,Packages & Summary
Video
00:09:04
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
00:09:45
SV Memories - Dynamic Arrays & Queues
Video
00:07:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
00:13:19
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
00:11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
00:09:52
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
00:18:44
SV Interfaces - Modports & Clocking Block
Video
00:18:30
SV Interfaces - Examples & Summary
Video
00:20:49
Knowledge Check : Data Types
Exercise
Knowledge Check:Memories
Exercise
Knowledge Check : Tasks & Functions
Exercise
Knowledge Check:Interface & Clocking Block
Exercise
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
Object Oriented Programing in SystemVerilog
SV OOP - Introduction, Class Data Type & Objects
Video
00:15:05
SV OOP - Constructor, Null Object, Object assignments and copy
Video
00:17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
00:17:30
SV OOP - Introduction, Inheritance & Super
Video
00:20:50
SV OOP - Static properties & methods and Pass by ref
Video
00:15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
00:21:53
Knowledge Check: Basic OOP
Exercise
Knowledge Check: Advanced OOP
Exercise
Advanced SystemVerilog
SV Randomization - Introduction, rand and randc
Video
00:10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
00:12:52
SV Randomization - Set Membership, Constraints & Summary
Video
00:13:22
SV Threads , Events, Mailbox and Semaphores
Video
00:23:11
SV Virtual Interface - Introduction, Implementation & Examples
Video
00:17:21
SV Functional Coverage - Introduction & CRCDV
Video
00:15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
00:17:30
Testbench Architecture and Verification Flow
Video
00:08:12
Transaction and Generator
Video
00:10:55
Interface and Drivers
Video
00:13:10
Monitors
Video
00:08:56
Scoreboard and Reference Model
Video
00:12:59
Environment and Testcases
Video
00:13:16
Knowledge Check: Randomization
Exercise
Knowledge Check : Virtual Interface
Exercise
Knowledge Check : Threads , Events, Semaphore & Mailbox
Exercise
Knowledge Check : Functional Coverage
Exercise
SV Assignment
PDF
Submit your SV Assignment here
Assignment
SystemVerilog Assertions
What are Assertions?
Video
00:13:07
Necessity of using SystemVerilog Assertions
Video
00:14:46
Types of Assertions
Video
00:14:55
SVA Building Blocks
Video
00:17:34
System Functions
Video
00:11:48
How to write sequences?
Video
00:11:21
Implication Operators
Video
00:24:34
Exercise based on Implication Operators and Timing Windows
Video
00:14:18
Repetition Operators
Video
00:21:46
Sequence Composition
Video
00:19:46
Methods for Sequences
Video
00:07:21
Miscellaneous Concepts in SVA
Video
00:07:27
Connecting Assertions to DUT
Video
00:07:59
SVA - Knowledge Check - 1
Exercise
SVA - Knowledge Check - 2
Exercise
SVA - Knowledge Check - 3
Exercise
SVA - Knowledge Check - 4
Exercise
SVA - Knowledge Check - 5
Exercise
SystemVerilog & SVA Labs
Lab Manual
PDF
Reference Material
Verification Methodology
PDF
Sv Language Concepts
PDF
SystemVerilog
PDF
SystemVerilog Assertions
PDF
ISA 1 - QP with Solutions (SV)
PDF
Practice questions - ISA2
PDF
ISA 2 - QP with Solutions
PDF
Practice Question - ESA
PDF
Interview Questions - SV
Mock Interview SV and UVM Questions_December-2025
PDF
Sample Interview Questions - April to June 2024
PDF
Sample Interview Questions - Jan to Mar 2024
PDF
Sample Interview Questions - Oct to December 2023
PDF
Sample Interview Questions - July to September 2023
PDF
Sample Interview Questions - Apr to June 2023
PDF
Sample Interview Questions - Jan to March 2023
PDF
Executive MTech - AI Accelerator Design
2 Exercises • 28 Learning Materials
Feedback form
Feeback form - Mtech AI
feedback_form
Basic Mathematics for Machine Learning
AI Accelerator Introduction
PDF
Basic Mathematics for Machine Learning
PDF
TCL
Introduction to Tcl-1
PDF
Introduction to TCL-2
PDF
Introduction to Tcl
Video
00:15:29
Control Flow Statements
Video
00:26:26
Procedures
Video
00:17:05
Data types - Strings
Video
00:15:16
Mathematical Operators
Video
00:14:00
Datatypes - Lists
Video
00:19:45
Data types - Arrays
Video
00:11:38
Data types - Dictionaries
Video
00:10:23
Practice Applications
Video
00:11:47
TCL
Video
00:05:45
Tcl manual
PDF
Introduction to Machine Learning
Introduction to ML
PDF
AI Accelerator Architecture Design
AI Accelerator Architecture Design
PDF
Unit 3 – Reference Material
PDF
AI Accelerator Assignment
Assignment
Submit your AI Assignment here
Assignment
Sample Questions for AI - ISA 2
PDF
Techniques for Hardware Optimized Inference & Emerging Tech for AI Accelerator
Reference Materials - AI
Unit 1 – Math Examples
PDF
CNN Examples
PDF
ISA 1 - QP with Solutions
PDF
CNN_RNN_Codes
PDF
ISA 2 - QP with Solutions
PDF
Model QP - ESA - AI Accelerator Design
PDF
Unit 1 - Practice Questions
PDF
Unit 2 - Practice Questions
PDF
Executive MTech - Next Generation IC Manufacturing, Packaging and Testing
8 Learning Materials
Reference Materials
Next Generation IC Manufacturing, Packaging and Testing
PDF
ICM Delivery PPts
Class 1a Course Info & Preview
PDF
Class 1b - Intro & Crystal Growth
PDF
Class 2a - Epitaxy
PDF
Class 2b - Oxidation
PDF
Class 3 and 4 - Lithography
PDF
Class 5a - Etch
PDF
Class 5b - Deposition
PDF
Executive MTech - UVM for Digital and AMS Verification
12 Exercises • 47 Learning Materials
Reference Materials
UVM for Digital and AMS Verification
PDF
UVM_Lab_Manual
PDF
Universal Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Verification Methodologies & Summary
Video
00:27:11
Constraint Random Coverage Driven Verification
Video
00:25:37
Knowledge Check : Verification Methodology Overview
Exercise
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
00:13:48
UVM Base Class Hierarchy
Video
00:14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
00:11:19
UVM Factory - Registration Process
Video
00:06:02
UVM Factory - Create Method and Factory Overriding
Video
00:11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
00:10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
00:10:41
UVM - TB Overview
Video
00:10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
00:16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
00:13:13
UVM Reporting Mechanism
Video
00:15:01
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
00:11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
00:13:01
UVM Configuration - Introduction to Configuration Facility
Video
00:13:02
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
00:09:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
00:15:01
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
00:16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
00:11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
00:15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
00:13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
00:08:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
00:09:23
UVM Events
Video
00:09:06
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
00:09:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM Labs
UVM Lab Manual
PDF
Lab1 Solution : Stimulus Modeling
Video
00:16:02
Lab2 Solution : Factory Overriding
Video
00:08:19
Lab3 Solution : UVM Phases
Video
00:10:22
Lab4 Solution : Creating UVM agent
Video
00:11:44
Lab5 Solution : UVM Sequences
Video
00:13:22
Lab6 Solution : Virtual Interface
Video
00:05:50
Lab7 Solution : Agent Integration
Video
00:08:12
Lab8 Solution : UVM Scoreboard
Video
00:06:39
Lab9 Solution : SoC - UVM VE implementation
Video
00:08:41
Lab10 Solution : Coverage & Regression
Video
00:04:33
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
00:15:55
UVM RAL - Adapter, Predictor and Integration
Video
00:20:36
UVM RAL - Definition of Register Sequences
Video
00:11:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
00:48:14
Executive MTech - Physical Design and Validation of Complex SoCs
11 Exercises • 276 Learning Materials
Reference Materials
Physical Design and Validation of Complex SoCs
PDF
Lab Manal
PDF
Introduction to Physical Design
Introduction to VLSI Design
Video
00:06:19
Design Styles
Video
00:09:36
Partitioning
Video
00:05:12
Floorplanning
Video
00:05:34
Placement
Video
00:05:34
Clock Tree Synthesis [ CTS ]
Video
00:06:35
Routing
Video
00:04:21
Static Timing Analysis [ STA ]
Video
00:05:24
Knowledge Check : Introduction to VLSI
Exercise
Physical Design - Static Timing Analysis
Timing Analysis, STA, DTA, FalsePath, Multicycle Path
Video
02:07:29
STA in Digital Design Flow, Inputs and Outputs of STA Tools
Video
00:40:53
Clocks , Different Types of Clocks, Uncertainties With the Clock
Video
01:22:59
Timing Parameters In STA
Video
00:54:09
Recovery and Removal Times and PVT Corners and their effect on Cell Delays
Video
01:49:58
Setup and Hold Times
Video
01:20:54
Setup and Hold In Equality Equations
Video
01:21:11
What is PrimeTime
Video
01:57:07
PrimeTime Lab Manual
Video
00:06:31
OCV and CRPR
Video
01:23:41
Modelling of CMOS Logic Cells
Video
01:16:30
Different Techniques to improve timing
Video
01:51:11
Knowledge Check : STA
Exercise
STA: Reference Material
PDF
CMOS Design and Technologies
CMOS : An Introduction to CMOS
Video
00:15:39
CMOS : MOS Fundamentals - Part 1
Video
00:15:59
CMOS : MOS Fundamentals - Part 2
Video
00:20:22
CMOS : MOS Fundamentals - Part 3
Video
00:11:39
Reference Materials : CMOS
PDF
CMOS : MOS - IV Characteristics : Part 1
Video
00:16:06
CMOS : MOS - IV Characteristics : Part 2
Video
00:07:16
CMOS : MOS - IV Characteristics : Part 3
Video
00:13:35
CMOS : Inverter Design - Part 1
Video
00:15:30
CMOS : Inverter Design - Part 2
Video
00:21:40
CMOS : Inverter Design - Part 3
Video
00:14:33
CMOS : Combinational Circuits - Part 1
Video
00:13:27
CMOS : Combinational Circuits - Part 2
Video
00:16:22
CMOS : Logical Effort
Video
00:20:33
CMOS : Layout Design - Part 1
Video
00:15:55
CMOS : Layout Design - Part 2
Video
00:07:53
CMOS : Stick Diagrams
Video
00:21:34
CMOS : Alternatives to CMOS - Part 1
Video
00:13:01
CMOS : Alternatives to CMOS - Part 2
Video
00:15:34
CMOS : Alternatives to CMOS - Part 3
Video
00:16:32
PD_Tanner_Tool_video_1
Video
00:20:59
PD_Tannner_Tool_Video_2
Video
00:38:11
PD_Tanner_Tool_Video_3
Video
00:27:24
Tanner Tool Lab Manual
PDF
Synthesis and PDKs
Libraries and PDKs- Part 1
Video
00:18:38
Libraries and PDKs - Part 2
Video
00:10:25
Synthesis Concepts
Video
00:16:07
Synthesis Steps
Video
00:14:30
Synthesis Varients
Video
00:10:02
Synthesis : Reference Material
PDF
Libraries and PDKs : Reference Material
PDF
SDC : Reference Material
PDF
SDC Fundamentals
Video
00:08:45
Object Access Commands
Video
00:11:50
Understanding SDC - Break down sections and System Interfaces
Video
00:03:20
Set Driving Cells and Set Load Commands
Video
00:03:09
Clock Types - Timing Constraints and Design Rule Constraints
Video
00:08:39
Commands to create different types of clocks
Video
00:05:26
Defining Input and Output delays
Video
00:15:27
Clock Domain Crossing and Timing Exceptions
Video
00:09:16
Maximum Delay and Power Optimization Commands
Video
00:11:18
Knowledge Check : Synthesis and PDKs
Exercise
Primetime - Tool Demo and Lab Solutions
STA Labs Refernce Material
PDF
Introduction to Primetime Tool
Video
00:07:04
STA Process
Video
00:04:59
PrimeTime in the implementation flow
Video
00:07:37
Timing Analysis Flow in PrimeTime
Video
00:04:18
How to read and interpret the timing reports (Part-1)
Video
00:04:39
How to read and interpret the timing reports (Part-2)
Video
00:11:39
How to invoke PrimeTime and use it?
Video
00:09:06
How to setup PT Tool with various inputs?
Video
00:08:37
How to write tcl scripts to automate loading the inputs and report generation?
Video
00:05:27
How to run various reporting commands?
Video
00:10:30
How to use GUI and understand histogram?
Video
00:05:20
PrimeTime Lab Manual
PDF
Task_1_Restore_a_Prime_Time_Session
Video
00:09:45
Task_2_ Explore_some_helpful_commands
Video
00:07:00
Task_3_Validate_an_Existing_Prime_Time_Session
Video
00:08:37
Task_4_ Execute_the_Run_Script_and_Analyze_the_run
Video
00:08:15
Task_5_Analyze_STA_Reports
Video
00:10:48
Task_1_validate_constraints
Video
00:07:39
Task_2_Analyse_Timing_Report_for_Input_Delay_Constraint
Video
00:10:11
Task_3_Analyse_Timing_Report_for_Output_Delay_Constraint
Video
00:07:08
Task_1_Setup_PrimeTime_for_Lab3
Video
00:03:51
Task_2_Generate_Summary_Reports
Video
00:12:27
Task_3_Analyse_Timing_Reports_for_Setup_and_Hold
Video
00:12:36
Task_4_ Apply_the_Correct_Timing_Report_Switches
Video
00:08:04
Task_5_Identify_Half-Clock_Cycle_Paths
Video
00:06:50
Task 1 - Get to Know the Design Clocks
Video
00:14:01
Task 2 - Use the GUI to Report Clock Relationships
Video
00:18:11
Task 3 - Use the GUI to explore detail of timing paths
Video
00:11:15
Task 4 - Report a false violations
Video
00:10:00
Task 5 - Re-execute the run script to reduce violations
Video
00:03:10
Lab5 - Task1
Video
00:09:19
Lab5 - Task2
Video
00:16:04
Lab 06 : Task 1
Video
00:03:44
Lab 06 : Task 2
Video
00:03:32
Lab 06 : Task 3
Video
00:05:49
Lab 06 : Task 4
Video
00:03:56
Lab 07 : Task 1
Video
00:04:15
Lab 07 : Task 2
Video
00:15:35
Lab 07 : Task 3
Video
00:02:44
Lab 08 : Task 1
Video
00:08:21
Lab 08 : Task 2
Video
00:11:28
Lab 08 : Task 3
Video
00:03:07
Knowledge Checks : Primetime
Exercise
Physical Design - TCL
Introduction to Tcl-1
PDF
Introduction to TCL-2
PDF
Introduction to Tcl
Video
00:15:29
Control Flow Statements
Video
00:26:26
Procedures
Video
00:17:05
Data types - Strings
Video
00:15:16
Mathematical Operators
Video
00:14:00
Datatypes - Lists
Video
00:19:45
Data types - Arrays
Video
00:11:38
Data types - Dictionaries
Video
00:10:23
Practice Applications
Video
00:11:47
TCL
Video
00:05:45
Tcl : Knowledge Check
Exercise
Tcl manual
PDF
Floor Planning and Power Planning
Introduction to Floor Planning
Video
00:15:19
Floor Planning : Aspect Ratio Utilization
Video
00:15:09
Floor Planning : Macros
Video
00:17:30
Floor Planning : Blockages
Video
00:13:20
Knowledge Check : Floor planning
Exercise
Introduction to Power Planning
Video
00:14:32
Power Planning : Regions, Patterns, Extensions
Video
00:08:55
Power Planning : Mesh Pattern
Video
00:16:38
Power Planning : Strageic Connection
Video
00:21:46
Power planning : PNA
Video
00:05:22
Knowledge Check : Power planning
Exercise
Physical Design : Placement
Placement : An Introduction
Video
00:04:42
Goals of Placement
Video
00:13:12
Placement : Cost Components and flow
Video
00:15:13
Detailed Placement
Video
00:02:45
Congestion and Overflow
Video
00:21:05
Timing driven placement and strategies
Video
00:14:43
HFNS and Cloning
Video
00:09:59
Scan Chain Reordering
Video
00:07:58
Placement Qualification and Outputs
Video
00:07:41
Placement Flow Overview
PDF
Knowledge Check : Placement
Exercise
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:42
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:58
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:53
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:58
Clock Tree Synthesis
Clock Tree Synthesis - An Introduction
Video
00:09:52
Pre CTS
Video
00:18:26
CTS : What is clock
Video
00:07:04
CTS Cell Selection
Video
00:18:26
CTS : Reference Material
PDF
Physical Design : Routing
Routing : An Introduction
Video
00:14:55
Routing : Global Routing
Video
00:25:38
Routing : Detail Routing
Video
00:17:13
Knowledge Check: Routing
Exercise
Routing : Reference Material
PDF
Logic Equivalence Checking
Equivalence Checking
PDF
Fusion Compiler ( Design Implementation) : Tool Demo and Labs
Fusion Compiler : Design Implementation
Video
00:05:30
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:42
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:58
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:53
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:58
Fusion Compiler : Design Implementation - Lab 08A : Task 1
Video
00:12:26
Fusion Compiler : Design Implementation - Lab 08A : Task 2
Video
00:23:02
Fusion Compiler : Design Implementation - Lab 08A - Task 3
Video
00:14:29
Fusion Compiler : Design Implementation - Lab 08A - Task 4
Video
00:10:16
Fusion Compiler : Design Implementation - Lab 08A - Task 5
Video
00:13:17
Fusion Compiler : Design Implementation - Lab 08B - Task 1
Video
00:23:25
Fusion Compiler : Design Implementation - Lab 08B - Task 2
Video
00:07:20
Fusion Compiler : Design Implementation - Lab 08B - Task 3
Video
00:03:02
Fusion Compiler : Design Implementation - Lab 08B - Task 4
Video
00:09:51
Fusion Compiler : Design Implementation - Lab 08B - Task 5
Video
00:21:56
Fusion Compiler : Design Implementation - Lab 08B - Task 6
Video
00:17:32
Fusion Compiler : Design Implementation - Lab 08B - Task 8
Video
00:11:37
Fusion Compiler : Design Implementation - Lab 09 - Task 1
Video
00:06:15
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 1
Video
00:20:51
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 2
Video
00:14:25
Signoff
Video
00:05:49
ECO Flow
Video
00:03:07
ECO Flow In Fusion Compiler
Video
00:00:36
Timing ECOs
Video
00:02:24
Spare Cells
Video
00:00:53
Manual ECO Vs Automated ECOs
Video
00:02:12
ECO Fusion Work Flow
Video
00:04:16
Signoff_ECO_Flow
PDF
Fusion Compiler : Lab 10 - Task 1 & 2
Video
00:22:45
Knowledge Check : Signoff / ECO
Exercise
Fusion Compiler (Design Planning) : Tool Demo and Labs
Fusion Compiler : Compile Flow
Video
00:14:52
Fusion Compiler Lab Manual
PDF
Fusion Compiler : Introduction
Video
00:21:46
Fusion Compiler: Design Planning - Lab 01 : Task 02
Video
00:03:04
Fusion Compiler : Design Planning - Lab 01 : Task 03
Video
00:09:31
Fusion Compiler : Design Planning - Lab 01 : Task 04 to Task 06
Video
00:05:53
Fusion Compiler : Design Planning - Lab 01 : Task 07
Video
00:05:33
Fusion Compiler : Design Planning - Lab 01 : Task 08
Video
00:04:34
Fusion Compiler : Design Planning - Lab 01 : Task 09
Video
00:09:03
Fusion Compiler : Design Planning - Lab 01 : Task 10 & Task 11
Video
00:12:24
Fusion Compiler : Design Creation ( Reading RTL)
Video
00:19:23
Fusion Compiler : DMM
Video
00:10:09
Fusion Compiler : Design Planning - Lab 02 : Task 01
Video
00:05:31
Fusion Compiler : Design Planning - Lab 02 : Task 02
Video
00:22:49
Fusion Compiler : Design Planning - Lab 02 : Task 03
Video
00:10:26
Fusion Compiler : Design Planning - Lab 02 : Task 04
Video
00:07:33
Compile_Flow
Video
00:14:52
Fusion Compiler : Design Planning - Lab 03 : Task 1
Video
00:03:57
Fusion Compiler : Design Planning - Lab 03 : Task 2
Video
00:06:08
DFT_Flow
Video
00:03:15
Fusion Compiler : Design Planning - Lab 03 : Task 3
Video
00:07:12
Fusion Compiler : Design Planning - Lab 03 : Task 4
Video
00:05:16
Fusion Compiler : Design Planning - Lab 03 : Task 5
Video
00:10:21
Fusion Compiler : Design Planning - Lab 03 : Task 6
Video
00:17:15
Fusion Compiler : Design Planning - Lab 03 : Task 7
Video
00:14:08
Fusion Compiler : Design Planning - Lab 03 : Task 8
Video
00:07:26
Fusion Compiler : Design Planning - Lab 04 : Task 5
Video
00:19:08
Technology Setup
Video
00:17:02
Fusion Compiler : Design Planning - Lab 04 : Task 2
Video
00:08:36
Fusion Compiler : Design Planning - Lab 04 : Task 1
Video
00:05:33
Fusion Compiler : Design Planning - Lab 04 : Task 3
Video
00:05:52
Auto_Floorplan
Video
00:19:06
Fusion Compiler : Design Planning - Lab 04 : Task 4
Video
00:07:33
MCMMM - Part 1
Video
00:29:51
MCMMM - Part 2
Video
00:18:45
CCD - Part 1
Video
00:21:03
CCD - Part 2
Video
00:07:09
CCD - part 3
Video
00:18:17
Fusion Compiler : Design Planning - Lab 05 : Task 1
Video
00:13:18
Fusion Compiler : Design Planning - Lab 05 : Task 2
Video
00:11:19
Fusion Compiler : Design Planning - Lab 05 : Task 3
Video
00:15:21
Fusion Compiler : Design Planning - Lab 05 : Task 4
Video
00:07:38
ICGs - Part 1
Video
00:17:06
ICGs - Part 2
Video
00:18:21
ICGs - Part 3
Video
00:07:05
ICGs - Part 4
Video
00:16:33
ICGs - Part 5
Video
00:12:38
Fusion Compiler : Design Planning - Lab 06 : Task 1
Video
00:25:10
Fusion Compiler : Design Planning - Lab 06 : Task 2
Video
00:15:46
Fusion Compiler : Design Planning - Lab 06 : Task 3
Video
00:09:23
Signal Integrity and Cross Talk
Introduction to SI and CT
Video
00:07:53
Reasons for Signal Integrity and Crosstalk
Video
00:13:52
Impact of Lateral and Interlayer Capacitance
Video
00:13:31
Understanding the Noise Margin
Video
00:15:54
Crosstalk Effects
Video
00:06:00
Crosstalk Mechanisms
Video
00:07:15
Noise Protection Techniques for SI and CT
Video
00:12:32
Signal Integrity and Crosstalk : Reference Material
PDF
Physical Verification
Physical Verification : Introduction
Video
00:10:05
Physical Verification : DRC
Video
00:12:24
Physical Verification : LVS
Video
00:08:56
Physical Verification : PERC - Part 1
Video
00:11:42
Physical Verification : PERC - Part 2
Video
00:15:22
Physical Verification : PERC - Part 3
Video
00:22:13
Physical Verification : PERC - Part 4
Video
00:13:14
Physical Verification : PERC - Part 5
Video
00:14:09
Knowledge Check - Physical Verification
Exercise
Physical Verification : DRC & LVS - Reference Material
PDF
Physical verification : Calibre PERC - Reference Material
PDF
Physical Verification Using Calibre Tool - Lab Manual
PDF
Introduction to Calibre GUI
Video
01:06:07
Calibre - Lab 1
Video
00:32:48
Calibre - lab 2
Video
00:23:04
Calibre - Lab 3 & 4
Video
00:18:13
Calibre Tool Demo - Physical Verification
Video
00:05:30
Calibre Tool Demo - Design Rules
Video
00:12:56
Calibre Tool Demo - Calibre DRC Flow
Video
00:05:04
Calibre Tool Demo - Solving DRC using Calibre nmdrc tool
Video
00:05:27
Calibre Tool Demo - Layout Versus Schematic
Video
00:06:01
Calibre Tool Demo -Calibre nmlvs Flow
Video
00:11:46
PD - Implementation Flow Guidelines
PD Flow Implementation Guidelines
PDF
Physical Design Implementation on Wally Core SoC
CVW Synthesis Specs
PDF
CVW PNR Manual
PDF
Course Instructor
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