Advanced VLSI Design and Verification - Online
Start learning VLSI Design and Verification, from anytime, anywhere - a complete self-paced online learning course
Course Instructor
Sweety Dharamdasani
To purchase this course, please contact the admin
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Course Overview
This is a self paced course which caters learning on VLSI Design and Verification.
Schedule of Classes
Course Curriculum
19 Subjects
Blended VLSI - M1 - Introduction to VLSI
1 Exercises • 5 Learning Materials
Introduction to VLSI
Why SoC?
Video
17:12
Mobile SoC Architecture
Video
9:35
SoC Design Process
Video
19:00
Moores Law, ASIC Vs FPGA
Video
15:10
VLSI Design Flow
Video
35:32
Knowledge Check : Introduction to VLSI
Exercise
Blended VLSI - M2 - Advanced Digital Design
15 Exercises • 41 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
13:26
Number System and Codes
Introduction to Number Systems and Codes
Video
37:45
Number Systems
Video
27:9
Codes
Video
10:9
Assignment 1 - Number Systems & Codes
PDF
Solution to Assignment 1 - Number Systems & Codes
Video
1:1:52
Knowledge Check : Number Systems and Codes
Exercise
Logic Circuits
Logic Circuits
Video
55:7
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Assignment 2 - Boolean Algebra & Logic Gates
PDF
Solution to Assignment 2 - Boolean Algebra & Logic Gates
Video
1:40:17
Combinational Circuits - Basics
Combinational Circuits - I
Video
28:25
Knowledge Check : Combinational Circuits - Basics- I
Exercise
Combinational Circuits - II
Video
44:8
Knowledge Check : Combinational Circuits - Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
21:8
Combinational Logic Circuits - Delays
Video
9:11
Encoders, decoders and Magnitude Comparators
Video
11:41
Multiplexers and Demultiplexers
Video
18:58
Universal Logic Gates and Tristate Buffers
Video
8:37
Summary & Knowledge Check
Video
25:42
Solution to Assignment 3 - Combinational Logic Circuits
Video
1:35:39
Assignment 3 - Combinational Logic Circuits
PDF
Knowledge Check : Combinational Circuits - Advanced-1
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
13:16
Assignment - 4 Latches & Flipflops
PDF
Solution to Assignment - 4 Latches & Flipflops
Video
1:012
Knowledge Check : Sequential Circuits : Advanced -1
Exercise
Registers & Counters
Video
37:19
Sequence Generators & Frequency dividers
Video
26:2
Assignment - 5 Registers & Counters
PDF
Solution to Assignment - 5
Video
1:13:2
Knowledge Check : Sequential Circuits : Advanced -2
Exercise
Finite State Machine FSM - Basics
FSM
Video
37:39
Knowledge Check : FSM - Basic
Exercise
FSM - Advanced
Finite State Machines - Part - 1
Video
27:44
Finite State Machines - Part - 2
Video
21:43
Assignment - 6 Finite State Machines
PDF
Solution to Assignment - 6
Video
1:1:5
Knowledge Check : Finite State Machines - Advanced
Exercise
Memories
Memories
Video
25:54
Knowledge Check :Memories -1
Exercise
Memories & PLD
Video
29:45
Assignment - 7 Memories, FIFO, Glitches & PLD
PDF
Solution to Assignment - 7
Video
21:50
Knowledge Check : Memories, Glitches and PLD)
Exercise
Digital Design Reference Book - Download FYR
Digital Design Reference Book
PDF
Advanced Digital Reference Book
PDF
Digital Module Test
Module Test : Digital
Exercise
Blended VLSI - M3 - Static Timing Analysis
5 Exercises • 13 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Video
7:40
Types of Timing Analysis
Video
10:22
False Paths & Multi Cycle Paths
Video
19:36
STA in Design Flow
Video
5:24
Knowledge Check : Introduction to STA
Exercise
STA: Clock
Clock - Part -1
Video
17:35
Clock - Part - 2
Video
17:41
Knowledge Check - Clock
Exercise
STA : Timing Parameters
Timing Parameters in STA - Part-1
Video
15:49
Timing Parameters in STA - Part-2
Video
13:58
Timing Parameters in STA - Part-3
Video
10:24
Knowledge Check - Timing Parameters
Exercise
STA : Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Video
18:30
Timing Analysis on Sequential Circuits - Part-2
Video
12:48
STA Procedure
Video
10:27
Knowledge Check - Timing analysis Procedure
Exercise
STA - Techniques to Improve Timing
Different Techniques to improve timing
Video
12:51
Knowledge Check - Techniques to Improve Timing
Exercise
Blended VLSI - M4 - Linux , Labs and VPN
2 Exercises • 7 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
Video
1:15:00
vi Text Editor
Video
31:00
Knowledge check: Linux
Exercise
Labs User Guide & VPN Configuration Guide
Linux Labs User Guide
PDF
VPN_Configuration_Guide
PDF
Linux Lab Manual
PDF
Linux Lab 1 : Solution
Video
8:26
Linux Lab 2 : Solution
Video
5:15
M4 - Linux - Module Test
Module Test : M4 - Linux
Exercise
Blended VLSI - M5 - Verilog HDL
9 Exercises • 53 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
12:1
Introduction to Verilog HDL
Video
23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
30:4
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
30:6
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
29:7
Knowledge Check - Verilog for Verification
Exercise
Compiler Directive
Compiler Directive
Video
17:27
Assignments
Assignments
Video
23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Verilog HDL Summary
Video
23:58
Verilog RTL Coding Examples
Video
28:40
Verilog Labs
Must read Instruction manual
PDF
Instructions - Verilog Labs
PDF
EDA Tools - Installation Guide
Video
18:50
Virtualbox_Ubuntu - Installation Guide
Video
20:17
Xilinx ISE Installation guide for Ubuntu
PDF
Installation guide for Virtual Box and Ubuntu in Windows
PDF
Verilog Labs
ZIP
EDA Tools - User Guide
Video
5:22
Solution to Lab1
Video
22:2
Solution to Lab 2
Video
17:12
Solution to Lab 3
Video
11:57
Solution to Lab 4
Video
6:53
Solution to Lab 5
Video
6:41
Solution to Lab 6
Video
8:18
Verilog_lab_manual_modelsim_quartus
PDF
Verilog Assignments
Verilog Assignment - 1
PDF
Solution to Verilog Assignment - 1
Video
10:12
Verilog Assignment - 2
PDF
Solution to Verilog Assignment - 2
Video
8:13
Verilog Assignment - 3
PDF
Solution to Verilog Assignment - 3
Video
11:57
Verilog Assignment - 4
PDF
Solution to Verilog Assignment - 4
Video
15:14
Assignment - 5 Structured Procedures
PDF
Solution to Verilog Assignment 5
Video
10:16
Assignment - 6Finite state machines
PDF
Solution to Verilog Assignment 6
Video
11:58
Verilog - Module test
Verilog Module Test
Exercise
Router 1x3 RTL design
Router_1x3_design_document
PDF
Introduction to Router
Video
10:53
Router Top Packet Structure
Video
7:16
Input Output Protocol
Video
4:40
Router Architecture
Video
19:17
Extra Reference Books
Linting using VC Spyglass - Reference Book
PDF
Logic Synthesis using DesignCompiler - Reference Book
PDF
Blended VLSI - M6 - Advanced Verilog&Code Coverage
5 Exercises • 17 Learning Materials
Advanced Verilog
Timescale system task & localparm
Video
14:48
Generate block & Continuous Procedural Assignments
Video
18:37
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
15:34
Named Events and Stratified Event Queue
Video
19:56
Knowledge Check- Advance Verilog 2
Exercise
Knowledge Check : Design Compiler
Exercise
Knowledge Check: RTL Linting
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
6:54
Statement and branch coverage
Video
7:17
Condition & Expression Coverage
Video
7:6
Toggle & FSM Coverage
Video
7:47
Questasim commands for Code Coverage
Video
11:26
Makefile for Simulations
Video
8:36
Knowledge Check-Code Coverage 1
Exercise
Code Coverage - Reference Book
Code Coverage Reference Book
PDF
Advanced Verilog & Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual - Questasim
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
19:5
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
25:16
Router Project Reference Material
Router_1x3_design_document
PDF
Blended VLSI - M7 - FPGA Architecture
2 Exercises • 2 Learning Materials
FPGA Architecture
FPGA - Lecture 1
Video
25:40
Knowledge Check - FPGA 1
Exercise
FPGA - Lecture 2
Video
28:10
Knowledge Check - FPGA 2
Exercise
Blended VLSI - M8 - CMOS Fundamentals
2 Exercises • 4 Learning Materials
CMOS Fundamentals
CMOS - Lecture 1
Video
30:50
CMOS - Lecture 2
Video
33:46
CMOS - Lecture 3
Video
23:45
CMOS Reference Book
CMOS Reference Book
PDF
Knowledge Check - CMOS
Knowledge Check - CMOS
Exercise
Module Test : CMOS
Knowledge Check - CMOS
Exercise
Blended VLSI - M9 - RISC-V
3 Exercises • 23 Learning Materials
RISC-V Instruction Set Architecture
Why RISC-V Processor?
Video
6:50
RISC-V processor overview
Video
10:24
RISC-V ISA Overview
Video
12:13
RV32I R Type Instruction
Video
9:29
RV32I I Type Instruction
Video
7:47
RV32I S and B Type Instructions
Video
11:55
RV32I J and U Type Instructions
Video
12:35
RV32I Assembly Programs and Summary
Video
19:22
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
8:36
RISC-V Register File and RV32I Instructions Format
Video
12:52
RV32I R Type ALU Datapath
Video
9:29
RV32I I Type ALU Datapath
Video
6:33
RV32I S Type ALU Datapath - Load & Store
Video
13:4
RV32I B Type ALU Datapath
Video
8:23
RV32I J Type ALU Datapath JAL & JALR
Video
9:26
RV32I U Type ALU Datapath and Summary
Video
10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
16:3
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
Project: RISC-V RV32I 5 stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
MSRV32I Core Design Specification
PDF
Blended VLSI -M10- ASIC Verification Methodologies
1 Exercises • 6 Learning Materials
ASIC Verification Methodology Overview
Introduction to Verification Methodology
Video
22:25
Verification Process
Video
21:46
Reusable TB
Video
7:24
Verification Environment Architecture
Video
19:2
Constraint Random Coverage Driven Verification
Video
25:37
Verification Methodologies & Summary
Video
27:11
Knowledge Check : Verification Methodology Overview
Exercise
Blended VLSI - M11 - SystemVerilog HVL
12 Exercises • 70 Learning Materials
SystemVerilog Language Concepts
SV Concepts Agenda
Video
6:38
SV Overview
Video
11:16
SV Transactions
Video
14:46
SV Interface
Video
14:51
SV Virtual Interface
Video
11:40
SV OOP
Video
13:56
SV Randomization & Functional Coverage
Video
6:47
SV TB Architecture
Video
10:19
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
10:50
SV Data Types - 2 State, Struct & Enum
Video
15:27
SV Data Types - Strings,Packages & Summary
Video
9:4
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
9:45
SV Memories - Dynamic Arrays & Queues
Video
7:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
13:19
Knowledge Check:Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
9:52
Knowledge Check : Tasks & Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
18:44
SV Interfaces - Modports & Clocking Block
Video
18:30
SV Interfaces - Examples & Summary
Video
20:49
Knowledge Check:Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
15:5
SV OOP - Constructor, Null Object, Object assignments and copy
Video
17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
17:30
Knowledge Check: Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
20:50
SV OOP - Static properties & methods and Pass by ref
Video
15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
21:53
Knowledge Check: Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
12:52
SV Randomization - Set Membership, Constraints & Summary
Video
13:22
Knowledge Check: Randomization
Exercise
SystemVerilog Threads
SV Threads, Events, Mailbox and Semaphores
Video
23:11
Knowledge Check : Threads , Events, Semaphore & Mailbox
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
17:30
Knowledge Check : Functional Coverage
Exercise
SystemVerilog Labs
SV Labs User Guide
PDF
Lab 1 Solution : Data Types
Video
17:56
Lab 2 Solution : Interfaces
Video
9:26
Lab 3 Solution : OOP Basics
Video
8:51
Lab 4 Solution : Advanced OOP
Video
18:9
Lab 5 Solution : Randomization
Video
5:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
22:2
Lab 7 Solution : Transaction
Video
9:43
Lab 8 Solution : Transactors
Video
9:1
Lab 9 Solution : Scoreboard & Reference Model
Video
10:59
Lab 10 Solution : Environment & Testcases
Video
11:20
SystemVerilog Lab Manual - for Synopsys VCS
PDF
Questasim - Tool Demos
Questasim- GUI and Batch Mode Usage
Video
23:10
Questasim - Coverage Report Generation
Video
10:11
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
10:14
Verdi Tool Demo - Part-1
Video
9:16
Verdi Tool Demo - Part-2
Video
7:48
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Video
10:18
Testbench Architecture and Verification Flow
Video
8:12
Transaction and Generator
Video
10:55
Interface and Drivers
Video
13:10
Monitors
Video
8:56
Scoreboard and Reference Model
Video
12:59
Environment and Testcases
Video
13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
10:45
SV - Module Test
Module Test : SV & SVA
Exercise
SV Assignments
Assignment 1
PDF
Solution to Assignment 1
Video
15:9
Assignment 2
PDF
Solution to Assignment 2
Video
24:45
Assignment 3
PDF
Solution to Assignment 3
Video
27:41
Assignment 4
PDF
Solution to Assignment 4
Video
29:54
Assignment 5
PDF
Solution to Assignment 5
Video
9:5
SV Mini Project
SV Mini Project (Verification of Counter RTL using SV)
PDF
Counter - TB Architecture and TB Components
Video
18:6
Blended VLSI - M12 - Business Communication
5 Exercises • 14 Learning Materials
Channels of Communication
Channels of Communication
Video
50:35
Channels of Communication
Exercise
Why and What of Interview
Lecture 1 - All about mindset
Video
13:56
Lecture 2 - How to ace a job interview?
Video
18:2
Telephone and Video Etiquette Tips for Online Interviews
Telephone and Video Etiquette
Video
27:15
Telephone and Video Etiquette
Exercise
Group Discussion
How to ace a Group discussion?
Video
19:43
Impression Management
Impression Management at Work Place
Video
31:57
Impression Management
Exercise
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
50:11
Professionalism
Professionalism, Gender and Culture Sensitivity
Video
25:35
Team Work
Video
8:11
Create a winning LinkedIn Profile
How to create a winning LinkedIn profile?
Video
37:57
Workplace Awareness
Getting Job Ready
Video
34:55
Email Etiquette
Email Writing - Tips and Tricks
Video
36:17
Email Etiquette
Exercise
Interpersonal Skills
Key behavioral skills for your workplace
Video
34:27
Interpersonal Skills
Exercise
Unsaid Rules of the workplace
Unsaid rules of the workplace
Video
38:53
Blended VLSI - M16 - Design Automation Perl
2 Exercises • 10 Learning Materials
PERL Scripting
PERL Scripting - Lecture 1
Video
48:16
Knowledge check:Perl1
Exercise
PERL Scripting - Lecture 2
Video
41:35
Knowledge check: Perl2
Exercise
PERL Reference Book
PERL Reference Book
PDF
PERL Labs
Perl Labs User Guide
PDF
PERL Lab Manual
PDF
Lab 01 Solution
Video
1:34
Lab 02 Solution
Video
1:19
Lab 03 Solution
Video
1:59
Lab 04 Solution
Video
2:15
Lab 05 Solution
Video
2:47
Blended VLSI -M17-Assertion Based Verification-SVA
6 Exercises • 21 Learning Materials
SVA Introduction & Types of Assertions
What are Assertions?
Video
13:7
Necessity of using SystemVerilog Assertions
Video
14:46
Types of Assertions
Video
14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks, System Functions
SVA Building Blocks
Video
17:34
System Functions
Video
11:48
SVA - Knowledge Check - 2
Exercise
Writing Sequences and Implication Operators
How to write sequences?
Video
11:21
Exercise based on Implication Operators and Timing Windows
Video
14:18
Implication Operators
Video
24:34
SVA - Knowledge Check - 3
Exercise
Repetition Operators and Sequence Composition
Repetition Operators
Video
21:46
Sequence Composition
Video
19:46
Methods for Sequences
Video
7:21
SVA - Knowledge Check - 4
Exercise
Miscellaneous Concepts and Connecting Assertions to DUT
Miscllenious Cocenpts in SVA
Video
7:27
Connecting Assertions to DUT
Video
7:59
SVA - Knowledge Check - 5
Exercise
SVA Assignments
SVA Assignment
PDF
Solution to SVA Assignment
Video
26:9
SVA Labs
SVA_Labs_User_Guide
PDF
SVA Lab Solution
Video
12:5
SVA Lab Manual - Synopsys VCS
PDF
SVA Reference Book
SVA Reference Book
PDF
SVA Case Study
Explanation to Project Specification
Video
38:5
Alarm Clock Project Specification
PDF
Knowledge Check : SVA
Knowledge Checks : SVA
Exercise
Blended VLSI M18Universal Verification Methodology
13 Exercises • 53 Learning Materials
Universal Verification Methodology Overview
Introduction to UVM
Video
10:47
UVM Concepts
Video
4:37
UVM SoC TB
Video
8:49
UVM AHB UVC
Video
7:8
UVM SoC TB Examples
Video
5:31
Knowledge Check : Introduction to UVM
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
13:48
UVM Base Class Hierarchy
Video
14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
11:19
UVM Factory - Registration Process
Video
6:2
UVM Factory - Create Method and Factory Overriding
Video
11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
10:41
UVM - TB Overview
Video
10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
13:13
UVM Reporting Mechanism
Video
15:1
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
13:1
UVM Configuration - Introduction to Configuration Facility
Video
13:2
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
9:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
15:1
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
8:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
9:23
UVM Events
Video
9:6
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
9:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
15:55
UVM RAL - Adapter, Predictor and Integration
Video
20:36
UVM RAL - Definition of Register Sequences
Video
11:55
Knowledge Check - UVM RAL
Exercise
UVM Labs
UVM Labs User Guide
PDF
Lab1 Solution : Stimulus Modeling
Video
16:2
Lab2 Solution : Factory Overriding
Video
8:19
Lab3 Solution : UVM Phases
Video
10:22
Lab4 Solution : Creating UVM agent
Video
11:44
Lab5 Solution : UVM Sequences
Video
13:22
Lab6 Solution : Virtual Interface
Video
5:50
Lab7 Solution : Agent Integration
Video
8:12
Lab8 Solution : UVM Socreboard
Video
6:39
Lab9 Solution : SoC - UVM VE implementation
Video
8:41
Lab10 Solution : Coverage & Regression
Video
4:33
UVM Lab Manual - Synopsys VCS
PDF
UVM Assignments
UVM Assignment 1
PDF
UVM Assignment 2
PDF
UVM Assignment 3
PDF
Solution to UVM Assignment 3
Video
15:39
Solution to UVM Assignment 1
Video
14:34
Solution to UVM Assignment 2
Video
15:1
UVM - Module Test
Module Test : UVM
Exercise
UVM Pilot Project (Router Verification)
Introduction
Video
7:6
Project : UVM TB Architecture
Video
15:54
Router Design
0 Exercises • 10 Learning Materials
Router 1x3 RTL Design
Router_1x3_design_document
PDF
Introduction to Router
Video
10:53
Router Top Packet Structure
Video
7:16
Input Output Protocol
Video
4:40
Router Architecture
Video
19:17
Router Design Solution Videos
Router_fifo
Video
20:58
Router_synchronizer
Video
14:6
Router_fsm
Video
17:17
Router_register
Video
20:58
Router_top
Video
19:4
Router Verification Project
0 Exercises • 4 Learning Materials
Router Specification and TB architecture
Introduction
Video
7:6
Project : UVM TB Architecture
Video
15:54
Router TB i Implementation
TB Implementation : TB Components - Build & Connect Phases
Video
23:50
TB Implementation : TB Components - Run Phases and Testcases for Regression
Video
26:11
RISC-V Project - DV
0 Exercises • 4 Learning Materials
RISC-V RV32I Quick reference Guides
RISC-V RV32I reference Card for V-Plan
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
RISC-V Specification
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
Questasim - Tool Demos
0 Exercises • 2 Learning Materials
Questasim - Tool Demos
Questasim- GUI and Batch Mode Usage
Video
23:10
Questasim - Coverage Report Generation
Video
10:11
Course Instructor
Sweety Dharamdasani
159 Courses • 3014 Students
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