Blended VLSI Design
Explore Maven Silicon's Blended VLSI Design course for advanced proficiency in theory and hands-on practice.
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Course Instructor
Maven Silicon
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Course Overview
Welcome to the Blended VLSI Design course – a comprehensive program covering various aspects of VLSI design. This course is divided into multiple modules to provide you with a holistic understanding of VLSI, from the basics to advanced topics. Explore the diverse modules and exercises to enhance your skills and knowledge. Let's embark on this blended journey through the world of VLSI design!
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Maven Silicon
252 Courses • 311108 Students
Course Curriculum
17 Subjects
VLSI - Design - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI & SoC Design
Electronic System
Video
26:43
Smartphone - SoC - Architecture
Video
9:55
SoC Design
Video
16:59
ASIC Vs FPGA
Video
12:7
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
13:4
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
9:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
9:5
ASIC Design Flow - Part-4 (DFT to STA)
Video
10:7
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
14:3
Semiconductor Industry
1 Exercises • 4 Learning Materials
Why Semiconductors?
Why Semiconductors?
Video
10:53
Semiconductor Supply Chain
Semiconductor Supply CHain
Video
12:31
Semiconductor Ecosystem
Semiconductor Ecosystem
Video
13:34
AI-driven Semiconductor Industry
AI-Driven
Video
7:21
Knowledge Check
Knowledge Check - Semiconductor Industry
Exercise
Must Read
2 Learning Materials
Onboarding & Platform Details
Must Knows
PDF
Admission Form
Admission Form
External Link
VLSI - Design -Advanced Digital Design
22 Exercises • 42 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
13:26
Number System and Codes
Introduction to Number Systems and Codes
Video
37:45
Number Systems
Video
27:9
Codes
Video
10:9
Assignment 1 - Number Systems & Codes
PDF
Submit your Digital Assignment - 1
Assignment
Solution to Assignment 1 - Number Systems & Codes
Video
1:1:52
Knowledge Check : Number Systems and Codes
Exercise
Logic Circuits
Logic Circuits
Video
55:7
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Assignment 2 - Boolean Algebra & Logic Gates
PDF
Submit your Digital Assignment -2
Assignment
Solution to Assignment 2 - Boolean Algebra & Logic Gates
Video
1:40:17
Combinational Circuits - Basics
Combinational Circuits - I
Video
28:25
Knowledge Check : Combinational Circuits - Basics- I
Exercise
Combinational Circuits - II
Video
44:8
Knowledge Check : Combinational Circuits - Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
21:8
Combinational Logic Circuits - Delays
Video
9:11
Encoders, decoders and Magnitude Comparators
Video
11:41
Multiplexers and Demultiplexers
Video
18:58
Universal Logic Gates and Tristate Buffers
Video
8:37
Summary & Knowledge Check
Video
25:42
Solution to Assignment 3 - Combinational Logic Circuits
Video
1:35:39
Assignment 3 - Combinational Logic Circuits
PDF
Submit your Digital Assignment -3
Assignment
Knowledge Check : Combinational Circuits - Advanced-1
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
13:16
Assignment - 4 Latches & Flipflops
PDF
Submit your Digital Assignment - 4
Assignment
Solution to Assignment - 4 Latches & Flipflops
Video
1:012
Knowledge Check : Sequential Circuits : Advanced -1
Exercise
Registers & Counters
Video
37:19
Sequence Generators & Frequency dividers
Video
26:2
Assignment - 5 Registers & Counters
PDF
Submit your Digital Assignment -5
Assignment
Solution to Assignment - 5
Video
1:13:2
Knowledge Check : Sequential Circuits : Advanced -2
Exercise
Finite State Machine FSM - Basics
FSM
Video
37:39
Knowledge Check : FSM - Basic
Exercise
FSM - Advanced
Finite State Machines - Part - 1
Video
27:44
Finite State Machines - Part - 2
Video
21:43
Assignment - 6 Finite State Machines
PDF
Submit your Digital Assignment -6
Assignment
Solution to Assignment - 6
Video
1:1:5
Knowledge Check : Finite State Machines - Advanced
Exercise
Memories
Memories
Video
25:54
Knowledge Check :Memories -1
Exercise
Memories & PLD
Video
29:45
Assignment - 7 Memories, FIFO, Glitches & PLD
PDF
Submit your Digital Assignment -7
Assignment
Solution to Assignment - 7
Video
21:50
Knowledge Check : Memories, Glitches and PLD)
Exercise
Digital Design Reference Book - Download FYR
Digital Design Reference Book
PDF
Advanced Digital Reference Book
PDF
Feedback Form - Digital
Feedback - Digital
External Link
Digital Module Test
Module Test : Digital
Exercise
VLSI - Design -Static Timing Analysis
5 Exercises • 6 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Video
7:40
Types of Timing Analysis
Video
10:22
False Paths & Multi Cycle Paths
Video
19:36
STA in Design Flow
Video
5:24
Knowledge Check : Introduction to STA
Exercise
STA: Clock
Clock - Part -1
Video
17:35
Clock - Part - 2
Video
17:41
Knowledge Check - Clock
Exercise
STA : Timing Parameters
Knowledge Check - Timing Parameters
Exercise
STA : Timing Analysis Procedure
Knowledge Check - Timing analysis Procedure
Exercise
STA - Techniques to Improve Timing
Knowledge Check - Techniques to Improve Timing
Exercise
VLSI - Design -Linux , Labs and VPN
2 Exercises • 7 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
Video
1:15:00
vi Text Editor
Video
31:00
Knowledge check: Linux
Exercise
Labs User Guide & VPN Configuration Guide
Linux Labs User Guide
PDF
VPN_Configuration_Guide
PDF
Linux Lab Manual
PDF
Linux Lab 1 : Solution
Video
8:26
Linux Lab 2 : Solution
Video
5:15
Module test
Module Test : M4 - Linux
Exercise
VLSI - Design - Verilog HDL
10 Exercises • 55 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Verilog_Course_Agenda
Video
14:12
VerilogHDL_Introduction
Video
28:35
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
30:4
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
30:6
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
29:7
Knowledge Check - Verilog for Verification
Exercise
Compiler Directive
Compiler Directive
Video
17:27
Assignments
Assignments
Video
23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Verilog HDL Summary
Video
23:58
Verilog RTL Coding Examples
Video
28:40
Synopsys DesignCompiler - Tool Demos
RTL Synthesis - Part-1
Video
17:26
RTL Synthesis - Part-2
Video
6:16
DC - Ultra
Video
2:23
Verilog Labs
Must read Instruction manual
PDF
Instructions - Verilog Labs
PDF
EDA Tools - Installation Guide
Video
18:50
VirtualBox_Ubuntu_Installation_on_windows
PDF
Xilinx ISE Installation Guide
PDF
Xilinx_Installation_video
Video
20:16
Verilog Lab Manual - Xilinx ISE
PDF
Verilog Labs
ZIP
EDA Tools - User Guide
Video
5:22
Solution to Lab1
Video
22:2
Solution to Lab 2
Video
17:12
Solution to Lab 3
Video
11:57
Solution to Lab 4
Video
6:53
Solution to Lab 5
Video
6:41
Solution to Lab 6
Video
8:18
Verilog Lab Manual - Modelsim and DC
PDF
Verilog_lab_manual_modelsim_quartus
PDF
Synopsys VC - Spyglass Lint - Tool Demo
VC Spyglass - Lint
Video
31:17
Verilog Assignments
Verilog Assignment - 1
PDF
Solution to Verilog Assignment - 1
Video
10:8
Verilog Assignment - 2
PDF
Solution to Verilog Assignment - 2
Video
8:13
Verilog Assignment - 3
PDF
Solution to Verilog Assignment - 3
Video
11:57
Verilog Assignment - 4
PDF
Solution to Verilog Assignment - 4
Video
15:14
Assignment - 5 Structured Procedures
PDF
Solution to Verilog Assignment 5
Video
10:16
Assignment - 6 Finite state machines
PDF
Solution to Verilog Assignment 6
Video
11:58
Extra Reference Books
Linting using VC Spyglass - Reference Book
PDF
Logic Synthesis using DesignCompiler - Reference Book
PDF
Feedback Form - Verilog Theory and Labs
Feedback Form - Verilog Theory & Labs
External Link
Verilog - Module test
Verilog Module Test
Exercise
Router 1x3 RTL design
Router_1x3_design - Specification
PDF
Introduction to Router
Video
10:53
Router Top Packet Structure
Video
7:16
Input Output Protocol
Video
4:40
Router RTL Design & Linting Report Submission
Assignment
Feedback Form - Router Design
External Link
Router Architecture
Video
19:17
VLSI - Design -Advanced Verilog&Code Coverage
5 Exercises • 17 Learning Materials
Advanced Verilog
Timescale system task & localparm
Video
14:48
Generate block & Continuous Procedural Assignments
Video
18:37
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
15:34
Named Events and Stratified Event Queue
Video
19:56
Knowledge Check- Advance Verilog 2
Exercise
Knowledge Check : Design Compiler
Exercise
Knowledge Check: RTL Linting
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
6:54
Statement and branch coverage
Video
7:17
Condition & Expression Coverage
Video
7:6
Toggle & FSM Coverage
Video
7:47
Questasim commands for Code Coverage
Video
11:26
Makefile for Simulations
Video
8:36
Knowledge Check-Code Coverage 1
Exercise
Code Coverage - Reference Book
Code Coverage Reference Book
PDF
Advanced Verilog & Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual - Questasim
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
19:5
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
25:16
Router Project - Specification
Router_1x3_design - Specification
PDF
VLSI - Design -FPGA Architecture
2 Exercises • 2 Learning Materials
FPGA Architecture
FPGA - Lecture 1
Video
25:40
Knowledge Check - FPGA 1
Exercise
FPGA - Lecture 2
Video
28:10
Knowledge Check - FPGA 2
Exercise
VLSI - Design -CMOS Fundamentals
2 Exercises • 4 Learning Materials
CMOS Fundamentals
CMOS - Lecture 1
Video
30:50
CMOS - Lecture 2
Video
33:46
CMOS - Lecture 3
Video
23:45
CMOS Reference Book
CMOS Reference Book
PDF
Knowledge Check - CMOS
Knowledge Check - CMOS
Exercise
Module Test : CMOS
Knowledge Check - CMOS
Exercise
VLSI - Design -RISC-V
3 Exercises • 23 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
9:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
9:15
RISC-V ISA Part-1 ( introduction)
Video
10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
20:42
Base ISA
Video
15:6
RV32I Base Instructions(R & I type)
Video
23:9
RV32I Base Instructions(S & B Type)
Video
23:30
RV32I Base Instructions(J Type)
Video
15:19
RV32I Base Instructions (U type)
Video
17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
8:36
RISC-V Register File and RV32I Instructions Format
Video
12:52
RV32I R Type ALU Datapath
Video
9:29
RV32I I Type ALU Datapath
Video
6:33
RV32I S Type ALU Datapath - Load & Store
Video
13:4
RV32I B Type ALU Datapath
Video
8:23
RV32I J Type ALU Datapath JAL & JALR
Video
9:26
RV32I U Type ALU Datapath and Summary
Video
10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
16:3
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
Business Communication
6 Exercises • 17 Learning Materials
Channels of Communication
Channels of Communication
Video
50:35
Channels of Communication
Exercise
Why and What of Interview
Lecture 1 - All about mindset
Video
13:56
Lecture 2 - How to ace a job interview?
Video
18:2
Telephone and Video Etiquette Tips for Online Interviews
Telephone and Video Etiquette
Video
27:15
Telephone and Video Etiquette
Exercise
Group Discussion
How to ace a Group discussion?
Video
19:43
Impression Management
Impression Management at Work Place
Video
31:57
Impression Management
Exercise
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
50:11
Technical content to be included in Resume for RN batches
PDF
Technical content to be included for PD batches
PDF
Upload your Resume for review
Assignment
Professionalism
Professionalism, Gender and Culture Sensitivity
Video
25:35
Team Work
Video
8:11