Blended VLSI Physical Design
Join Maven Silicon's Blended VLSI Physical Design course to learn physical design intricacies with a balanced mix of theory and hands-on experience.
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Course Instructor
Maven Silicon
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Course Overview
Welcome to the Blended VLSI Physical Design course – a comprehensive program covering key modules such as Physical Verification, Signal Integrity, Placement, DFT, STA, Floorplanning, Routing, Clock Tree Synthesis, Synthesis and PDKs, CMOS Devices, and Introduction to Physical Design. Delve into practical labs, tool demos, and reference materials to master the intricacies of VLSI physical design.
Course Curriculum
19 Subjects
VLSI - Physical Design -Introduction to Physical Design
1 Exercises • 8 Learning Materials
Introduction to Physical Design
Design Styles
Video
9:36
Partitioning
Video
5:12
Floor-planning
Video
5:34
placement
Video
5:34
CTS
Video
6:35
Routing
Video
4:21
Static Timing Analysis (STA)
Video
5:24
Knowledge Check : Introduction to PD
Exercise
Reference Book : Introduction to Physical Design
Introduction to Physical Design
PDF
VLSI - Physical Design -CMOS Devices and Technologies
1 Exercises • 16 Learning Materials
Introduction to CMOS
Introduction to CMOS
Video
7:41
MOS Fundamentals
MOS Fundamentals
Video
20:40
MOS IV Characteristics
MOS IV Characteristics
Video
46:43
CMOS Inverter Design
CMOS Inverter Design
Video
50:56
CMOS Design
CMOS Design_1
Video
50:43
CMOS Design_2
Video
55:13
Layouts and Stick Diagrams
What is Layout
Video
5:31
Layout of Inverter and Nand gates
Video
2:53
Lamda Based Rules
Video
3:27
Stick Diagrams
Video
5:22
Stick Diagrams Eulers Method
Video
3:27
Foundries
Foundries : Semiconductor Eco System
Video
45:16
Advancements In MOSFETs
Advancements In MOSFETs
Video
38:44
Tanner Lab Videos
PD_Tanner_Tool_video_1
Video
20:58
PD_Tannner_Tool_Video_2
Video
38:10
PD_Tanner_Tool_Video_3
Video
27:24
CMOS Lab Manual
Reference Book
Knowledge Check : CMOS
Knowledge Check : CMOS
Exercise
VLSI - Design - Design for Testability
1 Exercises • 20 Learning Materials
DFT Theory
Introduction to DFT
Video
11:15
Types of Testing
Video
8:24
Basic Testing Principles
Video
11:39
Fault Collapsing
Video
12:27
What is DFT?
Video
10:50
DFT Techniques - Ad-hoc Techniques
Video
10:15
DFT Techniques- Structured Techniques
Video
9:15
BIST & boundary Scan
Video
12:8
Introduction to BIST, LBIST & MBIST
Video
19:59
Knowledge check: DFT
Exercise
DFT Reference Book
DFT Reference Book
PDF
Tessent Shell - Introduction
Introduction to Tessent Shell
Video
3:37
System Modes
Video
3:13
TSDB
Video
5:23
DFT lab Solutions
Lab 01 : MBIST
Video
16:16
Lab 02 : DRC
Video
16:56
Lab 03 : Boundary Scan
Video
8:49
Lab 04 : Scan Chain
Video
9:23
Lab 05 : IJTAG
Video
16:40
Lab 06 : EDT
Video
10:6
DFT Lab Manual
PDF
VLSI - Physical Design -Synthesis and PDKs
2 Exercises • 24 Learning Materials
Libraries and PDKs
Process Design Kits (PDKs)
Video
10:24
NDM Libraries
Video
4:00
Library query
Video
026
Library file (.lib)
Video
1:40
Technology File (.tf)
Video
1:59
Layout Vs Frame View (lef Vs frame)
Video
3:12
Synthesis
SoC Design Flow -- Various abstraction levels
Video
4:19
What is Synthesis
Video
2:14
Synthesis Flow
Video
2:9
Knowledge Check : Synthesis and PDKs
Knowledge Check : Synthesis and PDKs
Exercise
Feedback Form - PD
Feedback Form - PD Theory & Labs
External Link
Defining Timing Constraints using SDC
Defining Timing Constraints Using SDC
Video
2:36
Why SDC is so Important
Video
3:1
Different Sections of SDC -- Header
Video
2:36
Timing Constraints -- Base Generated and Virtual Clocks
Video
5:24
System Interface Commands
Video
2:39
Design Rule Constraints
Video
1:43
Timing Constraints -- Group path Uncertainty Jitter Latency
Video
4:29
Timing Constraints -- set input delay and set output delay
Video
3:34
Clock Domain Crossing (CDC)
Video
4:42
Timing Exceptions
Video
4:45
SDC Commands Classification in Fusion Compiler
Video
2:16
Module Test : Intro to PD, CMOS , Synthesis & PDK and DFT
Module Test : Intro to PD, CMOS , Synthesis & PDK andDFT
Exercise
Reference Books
Ref: Synthesis
PDF
Ref: Libraries and PDKs
PDF
Ref: SDC
PDF
VLSI - Physical Design -Static Timing Analysis (PD)
3 Exercises • 15 Learning Materials
Timing Analysis, STA, DTA , False path and Multicycle Path
Timing Analysis, STA, DTA, FalsePath, Multicycle Path
Video
2:14:26
STA in Digital Design Flow, Inputs and Outputs of STA Tools
Video
44:18
Clocks , Different Types of clocks, Uncertainties with the Clock
Clocks , Different Types of Clocks, Uncertainties With the Clock
Video
1:25:2
Timing Parameters In STA
Timing Parameters In STA
Video
54:42
Recovery and Removal Times and PVT Corners and their effect on Cell Delays
Video
1:50:38
Setup and Hold Times
Setup and Hold Times
Video
1:21:26
Setup and Hold In Equality Equations
Video
1:21:53
What is Prime Time
What is PrimeTime
Video
1:57:38
PrimeTime Lab Manual
Video
7:34
OCV and CRPR
OCV and CRPR
Video
1:31:10
Modelling of CMOS Logic Cells
Modelling of CMOS Logic Cells
Video
1:19:9
Different Techniques to improve timing
Different Techniques to improve timing
Video
12:51
Knowledge Check : STA
Exercise
Knowledge Check : STA
Knowledge Check - STA
Exercise
Reference Book : STA
STA: reference Book
PDF
STA Assignment
STA Assignment 1
PDF
STA Assignment 2
PDF
Module Test 2 : STA, SDC, Primetime
Module Test 2 : STA, SDC, Primetime
Exercise
VLSI - Physical Design -Primetime - Tool Demo and Lab Solutions
1 Exercises • 30 Learning Materials
Primetime Tool Demo
Introduction to Primetime Tool
Video
7:4
STA Process
Video
4:59
PrimeTime in the implementation flow
Video
7:37
Timing Analysis Flow in PrimeTime
Video
4:18
How to read and interpret the timing reports (Part-1)
Video
4:39
How to read and interpret the timing reports (Part-2)
Video
11:39
How to invoke PrimeTime and use it?
Video
9:6
How to setup PT Tool with various inputs?
Video
8:37
How to write tcl scripts to automate loading the inputs and report generation?
Video
5:27
How to run various reporting commands?
Video
10:30
How to use GUI and understand histogram?
Video
5:20
PRIMETIME Lab - 1 Solutions
Task_1_Restore_a_Prime_Time_Session
Video
9:45
Task_2_ Explore_some_helpful_commands
Video
7:00
Task_3_Validate_an_Existing_Prime_Time_Session
Video
8:37
Task_4_ Execute_the_Run_Script_and_Analyze_the_run
Video
8:15
Task_5_Analyze_STA_Reports
Video
10:48
PRIMETIME Lab - 2 Solutions
Task_1_validate_constraints
Video
7:39
Task_2_Analyse_Timing_Report_for_Input_Delay_Constraint
Video
10:11
Task_3_Analyse_Timing_Report_for_Output_Delay_Constraint
Video
7:8
PRIMETIME Lab -3 Solutions
Task_1_Setup_PrimeTime_for_Lab3
Video
3:51
Task_2_Generate_Summary_Reports
Video
12:27
Task_3_Analyse_Timing_Reports_for_Setup_and_Hold
Video
12:36
Task_4_ Apply_the_Correct_Timing_Report_Switches
Video
8:4
Task_5_Identify_Half-Clock_Cycle_Paths
Video
6:50
PRIMETIME Lab - 4 Solutions
Task 1 - Get to Know the Design Clocks
Video
14:1
Task 2 - Use the GUI to Report Clock Relationships
Video
18:11
Task 3 - Use the GUI to explore detail of timing paths
Video
11:15
Task 4 - Report a false violations
Video
10:00
Task 5 - Re - execute the run script to reduce violations
Video
3:10
STA Lab Manual
PrimeTime Lab Manual
PDF
Knowledge Check : Primetime
Knowledge Checks : Primetime
Exercise
VLSI - Physical Design -Fusion Compiler (Design Planning) - Tool Demos and Lab Solutions
1 Exercises • 43 Learning Materials
Physical Design Using Fusion Compiler Lab Manual
Fusion Compiler Lab Manual
PDF
Introduction to Fusion Compiler
Introduction to Fusion Compiler
Video
8:44
Lab 1 : Using Fusion Compiler GUI (VNC Demo))
Fusion Compiler GUI VNC Demo
Video
15:9
Reading RTL and DMM
Reading RTL
Video
11:35
Design Mismatch Manager (DMM)
Video
5:36
Lab 2 : Reading RTL and DMM (VNC Demo)
Reading RTL and DMM
Video
10:35
Compile Flow
Compile flow -- compile_fusion command
Video
3:30
Seven stages of compile_fusion
Video
5:11
DFT Insertion
Video
2:32
Objects
Video
6:40
Application Options
Video
3:15
Attributes
Video
5:7
Lab 3: Compile Flow (VNC Demo)
Compile Flow VNC Demo
Video
15:00
Minimum Setup (Lab -4)
Minimum Setup - 1
Video
4:53
Minimum Setup - 2
Video
7:3
Minimum Setup - 3
Video
1:37
UPF and Auto Floorplan (Lab - 4)
Unified Power Format (UPF)
Video
2:38
Incomplete UPF Feature
Video
3:49
Minimum UPF Requirements
Video
2:33
Enable Incomplete UPF Feature
Video
2:36
Auto Floorplan
Video
5:18
Creating Voltage Areas
Video
2:50
Macro Placement
Video
2:4
Timing Setup(Lab - 4)
MCMM
Video
2:18
Creating Modes Corners and Scenarios
Video
4:44
Modes Corners and Scenario Constraints
Video
1:39
Loading Constraints
Video
4:49
Minimize Modes and Corners with Scenario analysis
Video
2:25
Reporting The Scenarios
Video
1:38
Lab 4 : Technology , UPF, Floorplan and Timing Setup (VNC Demo)
Lab4: Technology, UPF, Floorplan and Timing Setup
Video
10:12
Lab 5: Concurrent Clock and Data Optimization
Concurrent Clock and Data Optimization
Video
5:1
Clock Balance Point Delays
Video
4:36
CCD for Hold Scenarios and Sub critical paths
Video
2:40
Targeted CCD
Video
1:4
Restricting the Amount of CCD Skewing
Video
1:50
Ignoring IO Timing for Boundary Registers
Video
4:6
Useful Skews for Macros
Video
5:58
Useful Skew for Macros together with CCD Optimization
Video
2:58
Setup for CCD Optimization
Video
3:12
Lab 6: Clock Gating and ICGs
Power Optimization and ICGs
Video
4:16
Total Power Optimization
Video
4:59
Multibit Banking
Video
6:13
Self Gating
Video
7:8
Knowledge Check : Fusion compiler
Knowledge Check : Fusion compiler
Exercise
VLSI - Physical Design -Fusion Compiler (Design Implementation) - Tool Demos and Lab Solutions
1 Exercises • 19 Learning Materials
Lab 7 : Introduction to Floorplanning
Floorplanning and Powerplanning_VNC
Video
14:44
Setting Up CTS (Lab - 8a)
Implicit sink and Ignore Pins
Video
4:3
Explicit Sink Pin
Video
3:48
Explicit Ignore Pin
Video
2:10
Modes and corners for Exceptions
Video
1:8
Inter clock skew balancing
Video
1:21
With Vs Without Inter clock Balancing
Video
1:35
Preserving pre-existing cells on clock tree
Video
3:44
Non Default Rules
Video
4:22
NDRs for Root Internal and Sink nets
Video
4:36
Timing and DRC Constraints
Video
5:58
Signoff (Lab10)
Signoff
Video
5:49
ECO Flow
Video
3:7
ECO Flow In Fusion Compiler
Video
036
Timing ECOs
Video
2:24
Spare Cells
Video
053
Manual ECO Vs Automated ECOs
Video
2:12
ECO Fusion Work Flow
Video
4:16
Signoff_ECO_Flow
PDF
Knowledge Check : Signoff / ECO
Exercise
VLSI - Physical Design -Floorplanning
2 Exercises • 14 Learning Materials
Floorplanning
What is Floorplanning
Video
4:37
Die Size Estimation and Utilization
Video
2:45
Aspect Ratio
Video
4:28
Initialize Floorplanning
Video
1:52
Macros
Video
3:39
Good and Bad Floorplan
Video
3:20
Placement Blockages
Video
3:46
Guidelines for Good Floorplan
Video
1:43
Knowledge Check : Floorplan
Exercise
Reference Book : Floorplanning
Ref: FloorPlanning
PDF
Powerplanning
Powerplanning Introduction
Video
5:5
Power Network Synthesis
Video
10:40
Running PNS
Video
5:4
Power Calculations
Video
2:48
Reference Book : Powerplanning
Power Planning
PDF
Knowledge Check : Powerplanning
Knowledge Check : Powerplanning
Exercise
VLSI - Physical Design -Placement
1 Exercises • 8 Learning Materials
Placement
Introduction to Placement
Video
4:14
Placement Flow
Video
7:10
Routing Resources and Congestion
Video
4:30
Timing Vs Congestion Driven Placement
Video
5:47
Floorplan settings to reduce congestion
Video
2:26
HFNS Gate Sizing and Cloning Scan chain Reordering
Video
3:55
Knowledge Check : Placement
Exercise
Reference Book : Placement
Placement
PDF
Physical Only Cells
PDF
VLSI - Physical Design -Clock Tree Synthesis
1 Exercises • 7 Learning Materials
Clock Tree Synthesis
Clock Tree Synthesis - Concept
Video
2:50
Pre-CTS
Video
3:13
What is Clock
Video
2:20
What is Clock Tree Synthesis
Video
2:6
Skew Groups
Video
2:26
CTS Cell Selection
Video
6:26
Knowledge Check : Clock Tree Synthesis
Exercise
Reference Book : CTS
Reference Book : CTS
PDF
VLSI - Physical Design -Routing
2 Exercises • 4 Learning Materials
Routing
Routing
Video
2:16
Routing Flow
Video
3:37
Metal Layer Stacks
Video
1:57
Knowledge Check: routing
Exercise