Campus Connect Program
Empower your future with Maven Silicon's Campus Connect Program. Connect with industry leaders, learn VLSI essentials, and kickstart your career in semiconductor design.
4.6
(34 ratings)
Course Instructor
Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview
Embark on the comprehensive Campus Connect Program, covering key areas in VLSI and ASIC design. Dive into foundational concepts in "Advanced Digital Design," explore "RISC-V ISA & RV32I RTL Design," master "Verilog HDL," understand "FPGA Architecture," and delve into "Static Timing Analysis." Gain expertise in "System Verilog HDVL," System Verilog assertions, UVM, and DFT principles. Explore physical design processes, enhance business communication skills, and learn the SPI protocol. This program equips you with essential knowledge for a well-rounded understanding of VLSI.
Course Curriculum
13 Subjects
VLSI COE- M1 - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Video
26:43
Smartphone - SoC - Architecture
Video
9:55
SoC Design
Video
16:59
ASIC Vs FPGA
Video
12:7
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
13:4
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
9:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
9:5
ASIC Design Flow - Part-4 (DFT to STA)
Video
10:7
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
14:3
VLSI COE- M2 - Advanced Digital Design
8 Exercises • 10 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
13:26
Digital Design Reference Book - Download FYR
Digital Design Reference Book
PDF
Number System and Codes
Number Systems and Codes - Basics
Video
37:45
Knowledge Check : Number Systems and Codes
Exercise
Logic Circuits
Logic Circuits
Video
55:7
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Combinational Circuits
Combinational Circuits - I
Video
28:25
Knowledge Check : Combinational Circuits - I
Exercise
Combinational Circuits - II
Video
44:8
Knowledge Check : Combinational Circuits - 2
Exercise
Sequential Circuits
Sequential Circuits - I
Video
40:58
Knowledge Check : Sequential Circuits -1
Exercise
Sequential Circuits - II
Video
45:15
Knowledge Check : Sequential Circuits -2
Exercise
Finite State Machine FSM
FSM
Video
37:39
Knowledge Check : FSM
Exercise
Memories
Memories
Video
25:54
Knowledge Check :Memories -1
Exercise
VLSI COE- M3 - RISC-V ISA & RV32I RTL Design
3 Exercises • 26 Learning Materials
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
RISC-V Instruction Set Architecture
RISC-V Overview
Video
9:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
9:15
RISC-V ISA Part-1 ( introduction)
Video
10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
20:42
Base ISA
Video
15:6
RV32I Base Instructions(R & I type)
Video
23:9
RV32I Base Instructions(S & B Type)
Video
23:30
RV32I Base Instructions(J Type)
Video
15:19
RV32I Base Instructions (U type)
Video
17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
8:36
RISC-V Register File and RV32I Instructions Format
Video
12:52
RV32I R Type ALU Datapath
Video
9:29
RV32I I Type ALU Datapath
Video
6:33
RV32I S Type ALU Datapath - Load & Store
Video
13:4
RV32I B Type ALU Datapath
Video
8:23
RV32I U Type ALU Datapath and Summary
Video
10:18
RV32I J Type ALU Datapath JAL & JALR
Video
9:26
Knowledge Check : RISC-V RTL Architecture Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
16:3
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
13:51
Knowledge Check : RISC-V RV32I 5 Stage Pipelined RTL Design
Exercise
Project: RISC-V RV32I 5 stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
VLSI COE- M4- Verilog HDL
8 Exercises • 30 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
12:1
Introduction to Verilog HDL
Video
23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
30:4
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
30:6
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
29:7
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Verilog HDL Summary
Video
23:58
Verilog RTL Coding Examples
Video
28:40
Verilog Labs
Instructions - Verilog Labs
PDF
Verilog Lab Manual
PDF
EDA Tools - Installation Guide
Video
18:50
EDA Tools - User Guide
Video
5:22
Solution to Lab1
Video
22:2
Solution to Lab 2
Video
17:12
Solution to Lab 3
Video
11:57
Solution to Lab 4
Video
6:53
Solution to Lab 5
Video
6:41
Solution to Lab 6
Video
8:18
RISC-V RTL Design
ALU Design
Video
11:3
ALU Verification
Video
7:48
Integer file design
Video
7:12
Integer File Verification
Video
9:19
RISC-V RTL Design & Verification Part -1
Video
13:41
RISC-V RTL Design & Verification Part -2
Video
12:22
RISC-V RTL Design & Verification Part -3
Video
19:45
RISC-V RTL Design & Verification Part -4
Video
6:21
VLSI COE- M5- FPGA Architecture
1 Exercises • 4 Learning Materials
FPGA Architecture
FPGA - Lecture 1
Video
25:40
FPGA - Lecture 2
Video
28:10
Knowledge Check - FPGA
Exercise
Implementation using Xilinx Vivado
Simulation using Vivado
Video
5:55
Implementation using Vivado
Video
10:37
VLSI COE- M6 - Static Timing Analysis
6 Exercises • 14 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Video
7:40
Types of Timing Analysis
Video
10:22
False Paths & Multi Cycle Paths
Video
19:36
STA in Design Flow
Video
5:24
Knowledge Check - STA Introduction
Exercise
STA Reference Book
STA Reference Book
PDF
STA: Clock
Clock - Part -1
Video
17:35
Clock - Part - 2
Video
17:41
Knowledge Check - Clock
Exercise
STA : Timing Parameters
Timing Parameters in STA - Part-1
Video
15:49
Timing Parameters in STA - Part-2
Video
13:58
Timing Parameters in STA - Part-3
Video
10:24
Knowledge Check - Timing Parameters
Exercise
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Video
18:30
Timing Analysis on Sequential Circuits - Part-2
Video
12:48
STA Procedure
Video
10:27
Knowledge Check - Timing analysis Procedure
Exercise
STA : Techniques to Improve Timing
Different Techniques to improve timing
Video
12:51
Knowledge Check - Techniques to Improve Timing
Exercise
Module Test : STA
Module Test : STA
Exercise
VLSI COE- M7 - System Verilog HDVL
2 Exercises • 14 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Video
22:25
Verification Process
Video
21:46
Reusable TB
Video
7:24
Verification Environment Architecture
Video
19:2
Constraint Random Coverage Driven Verification
Video
25:37
Verification Methodologies & Summary
Video
27:11
Knowledge Check : Verification Methodology Overview
Exercise
SystemVerilog Language Concepts
SV Concepts Agenda
Video
6:38
SV Overview
Video
11:16
SV Transactions
Video
14:46
SV Interface
Video
14:51
SV Virtual Interface
Video
11:40
SV OOP
Video
13:56
SV Randomization & Functional Coverage
Video
6:47
SV TB Architecture
Video
10:19
Knowledge Check : SV language Concepts Overview
Exercise
VLSI COE- M8 - System Verilog Assertions
1 Exercises • 3 Learning Materials
SVA Introduction & Types of Assertions
What are Assertions?
Video
13:7
Necessity of using SystemVerilog Assertions
Video
14:46
Types of Assertions
Video
14:55
SVA - Knowledge Check - 1
Exercise
VLSI COE- M9 - Universal Verification Methodology
1 Exercises • 3 Learning Materials
Universal Verification Methodology Overview
UVM_Introduction
Video
43:18
Advanced_UVM_CaseStudies
Video
48:13
Knowledge Check : Introduction to UVM
Exercise
RISC-V Verification using UVM - Demo
RISC-V Verification using UVM - Demo
Video
31:33
VLSI COE- M10 - Design For Testability DFT
1 Exercises • 14 Learning Materials
Overview on DFT
Introduction to DFT
Video
11:15
Types of Testing
Video
8:24
Basic Testing Principles
Video
11:39
Fault Collapsing
Video
12:27
What is DFT?
Video
10:50
DFT Techniques - Ad-hoc Techniques
Video
10:15
DFT Techniques- Structured Techniques
Video
9:15
BIST & boundary Scan
Video
12:8
Introduction to BIST, LBIST & MBIST
Video
19:59
Knowledge check: DFT
Exercise
DFT - Project Demo
Introduction
Video
055
Boundary Scan
Video
8:4
Scan Chain Insertion
Video
7:43
ATPG
Video
7:44
EDT IP Core Insertion
Video
4:53
VLSI COE- M11 - Physical Design
23 Learning Materials
Physical Design Processes - Overview
Intro to VLSI
Video
6:19
Design Styles
Video
9:36
Partitioning
Video
5:12
Floor-planning
Video
5:34
placement
Video
5:34
CTS
Video
6:35
Routing
Video
4:21
Static Timing Analysis (STA)
Video
5:24
Physical Verification
physical_verification
Video
5:30
Design_Rules
Video
12:56
calibre_drc_flow
Video
5:4
How to solve DRC Using Calibre nmdrc tool
Video
5:27
Layout Versus Schematic
Video
6:1
calibre nmlvs flow
Video
11:46
Project Demo: RISC-V Design Implementation Using DC + ICC Tools
RISC – V IP Physical Design Implementation Using DC and ICC2
PDF
RISC-V QRG
PDF
RISC-V Implementation Using DC ICCII Flow
Video
3:32
Synthesis tcl script
Video
5:49
Synthesis Using DC - Running Script and Viewing Schematic
Video
2:24
Analysing area timing and Power reports
Video
2:1
Design setup and Floorplanning
Video
9:31
Power Planning
Video
4:8
Placement_CTS_Routing
Video
7:30
VLSI COE- M12 - Business Communication
5 Learning Materials
Business Communication Skills
Email Writing - Tips and Tricks
Video
36:17
Unsaid rules of the workplace
Video
38:53
Why and What of an Interview- All about the Mindset
Video
13:56
Telephone and Video Etiquette
Video
27:15
How to ace a job interview?
Video
18:2
VLSI COE - M13 - Protocols
1 Learning Materials
SPI Protocol
Project Explanation
Video
38:43
Course Instructor
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Maven Silicon
262 Courses • 326048 Students
Ratings & Reviews
4.6 /5
34 ratings
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FAQ's
1. What is the Campus Connect Program?
The Campus Connect Program bridges academia and industry, offering engineering students a comprehensive curriculum in VLSI and ASIC design. It focuses on skill development, hands-on training, and industry-relevant tools to enhance career readiness.
2. Why are skill development courses important for engineering students?
Skill development courses provide practical knowledge and industry-relevant skills, bridging the gap between academic learning and professional requirements. These courses make students more employable and prepared for real-world challenges.
3. What does the Campus Connect Program in VLSI include?
The Campus Connect Program in VLSI covers advanced digital design, Verilog HDL, RISC-V ISA, FPGA architecture, static timing analysis, physical design, and UVM. It equips students with technical expertise and professional skills needed in the VLSI industry.
4. How is VLSI training beneficial for students?
VLSI training provides hands-on experience with design tools, enhances understanding of complex chip design concepts, and prepares students for roles in the semiconductor industry, improving their employability.
5. How does industry-academia collaboration help students in VLSI?
Industry-academia collaboration ensures that students learn the latest technologies and practices in VLSI, making them industry-ready. It also provides opportunities for internships, projects, and real-world problem-solving.
6. What skills can students gain from development programs?
Students can gain technical skills in areas like VLSI design, programming, FPGA, and ASIC design, along with soft skills like communication and teamwork, enhancing their overall professional profile.
7. What is the purpose of VLSI workshops in campuses?
VLSI workshops introduce students to the fundamentals of chip design, verification, and physical design, providing a platform for practical learning and interaction with industry experts.
8. How does a campus-based VLSI certification benefit students?
A campus-based VLSI certification validates students' skills in semiconductor design, making them stand out in the job market and opening up more career opportunities in the VLSI domain.
9. Are internships included in the Campus Connect Program?
Yes, the program often includes internships, providing students with real-world experience in VLSI design and verification, along with exposure to industry practices.
10. What are corporate training partnerships with universities?
These partnerships involve collaboration between corporations and universities to design training programs that align with industry needs, helping students gain skills that are directly applicable in the workplace.
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