Campus Connect Program
Empower your future with Maven Silicon's Campus Connect Program. Connect with industry leaders, learn VLSI essentials, and kickstart your career in semiconductor design.
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Course Overview
Embark on the comprehensive Campus Connect Program, covering key areas in VLSI and ASIC design. Dive into foundational concepts in "Advanced Digital Design," explore "RISC-V ISA & RV32I RTL Design," master "Verilog HDL," understand "FPGA Architecture," and delve into "Static Timing Analysis." Gain expertise in "System Verilog HDVL," System Verilog assertions, UVM, and DFT principles. Explore physical design processes, enhance business communication skills, and learn the SPI protocol. This program equips you with essential knowledge for a well-rounded understanding of VLSI.
Course Curriculum
13 Subjects
VLSI COE- M1 - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Smartphone - SoC - Architecture
SoC Design
ASIC Vs FPGA
Knowledge Check : Introduction to VLSI
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
ASIC Design Flow - Part-2 (Architecture to RTL Design)
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
ASIC Design Flow - Part-4 (DFT to STA)
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
VLSI COE- M2 - Advanced Digital Design
8 Exercises • 10 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Digital Design Reference Book - Download FYR
Digital Design Reference Book
Number System and Codes
Number Systems and Codes - Basics
Knowledge Check : Number Systems and Codes
Logic Circuits
Logic Circuits
Knowledge Check : Logic Circuits and Boolean Algebra-1
Combinational Circuits
Combinational Circuits - I
Knowledge Check : Combinational Circuits - I
Combinational Circuits - II
Knowledge Check : Combinational Circuits - 2
Sequential Circuits
Sequential Circuits - I
Knowledge Check : Sequential Circuits -1
Sequential Circuits - II
Knowledge Check : Sequential Circuits -2
Finite State Machine FSM
FSM
Knowledge Check : FSM
Memories
Memories
Knowledge Check :Memories -1
VLSI COE- M3 - RISC-V ISA & RV32I RTL Design
3 Exercises • 26 Learning Materials
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I U Type ALU Datapath and Summary
RV32I J Type ALU Datapath JAL & JALR
Knowledge Check : RISC-V RTL Architecture Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V RV32I 5 Stage Pipelined RTL Design
Project: RISC-V RV32I 5 stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V RV32I - Quick Reference Guide for Instrcutions
VLSI COE- M4- Verilog HDL
8 Exercises • 30 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Style
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Instructions - Verilog Labs
Verilog Lab Manual
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab1
Solution to Lab 2
Solution to Lab 3
Solution to Lab 4
Solution to Lab 5
Solution to Lab 6
RISC-V RTL Design
ALU Design
ALU Verification
Integer file design
Integer File Verification
RISC-V RTL Design & Verification Part -1
RISC-V RTL Design & Verification Part -2
RISC-V RTL Design & Verification Part -3
RISC-V RTL Design & Verification Part -4
VLSI COE- M5- FPGA Architecture
1 Exercises • 4 Learning Materials
FPGA Architecture
FPGA - Lecture 1
FPGA - Lecture 2
Knowledge Check - FPGA
Implementation using Xilinx Vivado
Simulation using Vivado
Implementation using Vivado
VLSI COE- M6 - Static Timing Analysis
6 Exercises • 14 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
Knowledge Check - STA Introduction
STA Reference Book
STA Reference Book
STA: Clock
Clock - Part -1
Clock - Part - 2
Knowledge Check - Clock
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
Knowledge Check - Timing Parameters
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
Knowledge Check - Timing analysis Procedure
STA : Techniques to Improve Timing
Different Techniques to improve timing
Knowledge Check - Techniques to Improve Timing
Module Test : STA
Module Test : STA
VLSI COE- M7 - System Verilog HDVL
2 Exercises • 14 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Constraint Random Coverage Driven Verification
Verification Methodologies & Summary
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Transactions
SV Interface
SV Virtual Interface
SV OOP
SV Randomization & Functional Coverage
SV TB Architecture
Knowledge Check : SV language Concepts Overview
VLSI COE- M8 - System Verilog Assertions
1 Exercises • 3 Learning Materials
SVA Introduction & Types of Assertions
What are Assertions?
Necessity of using SystemVerilog Assertions
Types of Assertions
SVA - Knowledge Check - 1
VLSI COE- M9 - Universal Verification Methodology
1 Exercises • 3 Learning Materials
Universal Verification Methodology Overview
UVM_Introduction
Advanced_UVM_CaseStudies
Knowledge Check : Introduction to UVM
RISC-V Verification using UVM - Demo
RISC-V Verification using UVM - Demo
VLSI COE- M10 - Design For Testability DFT
1 Exercises • 14 Learning Materials
Overview on DFT
Introduction to DFT
Types of Testing
Basic Testing Principles
Fault Collapsing
What is DFT?
DFT Techniques - Ad-hoc Techniques
DFT Techniques- Structured Techniques
BIST & boundary Scan
Introduction to BIST, LBIST & MBIST
Knowledge check: DFT
DFT - Project Demo
Introduction
Boundary Scan
Scan Chain Insertion
ATPG
EDT IP Core Insertion
VLSI COE- M11 - Physical Design
23 Learning Materials
Physical Design Processes - Overview
Intro to VLSI
Design Styles
Partitioning
Floor-planning
placement
CTS
Routing
Static Timing Analysis (STA)
Physical Verification
physical_verification
Design_Rules
calibre_drc_flow
How to solve DRC Using Calibre nmdrc tool
Layout Versus Schematic
calibre nmlvs flow
Project Demo: RISC-V Design Implementation Using DC + ICC Tools
RISC – V IP Physical Design Implementation Using DC and ICC2
RISC-V QRG
RISC-V Implementation Using DC ICCII Flow
Synthesis tcl script
Synthesis Using DC - Running Script and Viewing Schematic
Analysing area timing and Power reports
Design setup and Floorplanning
Power Planning
Placement_CTS_Routing
VLSI COE- M12 - Business Communication
5 Learning Materials
Business Communication Skills
Email Writing - Tips and Tricks
Unsaid rules of the workplace
Why and What of an Interview- All about the Mindset
Telephone and Video Etiquette
How to ace a job interview?
VLSI COE - M13 - Protocols
1 Learning Materials
SPI Protocol
Project Explanation
Course Instructor
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Maven Silicon
248 Courses • 300529 Students
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