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Blended VLSI Verification

Enroll in Maven Silicon's Blended VLSI Verification course to gain expertise through a blend of theory and practical application.

4.8
(1252 ratings)
Course Instructor Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview

Welcome to the Blended VLSI Verification course – a comprehensive program that strategically blends key modules, including Universal Verification Methodology (UVM), Assertion-Based Verification (SVA), and SystemVerilog Hardware Verification Language (HVL). In the UVM module, delve into essential aspects such as UVM TB Architecture, Stimulus Modeling, and Sequencing. The SVA module introduces you to assertion-based verification, covering building blocks, system functions, and practical labs. SystemVerilog HVL is a pivotal module, encompassing language concepts, object-oriented programming, and functional coverage. This course is designed to equip you with practical skills alongside theoretical knowledge, preparing you for success in the dynamic field of VLSI verification.

Course Curriculum

8 Subjects

VLSI -Verification -ASIC Verification Methodologies

1 Exercises • 6 Learning Materials

ASIC Verification Methodology Overview

Introduction to Verification Methodology

Video
22:25

Verification Process

Video
21:46

Reusable TB

Video
7:24

Verification Environment Architecture

Video
19:2

Constraint Random Coverage Driven Verification

Video
25:37

Verification Methodologies & Summary

Video
27:11

Knowledge Check : Verification Methodology Overview

Exercise

VLSI -Verification - SystemVerilog HVL

12 Exercises • 71 Learning Materials

SystemVerilog Language Concepts

SV Concepts Agenda

Video
6:38

SV Overview

Video
11:16

SV Transactions

Video
14:46

SV Interface

Video
14:51

SV Virtual Interface

Video
11:40

SV OOP

Video
13:56

SV Randomization & Functional Coverage

Video
6:47

SV TB Architecture

Video
10:19

Knowledge Check : SV language Concepts Overview

Exercise

SystemVerilog Reference Book

SystemVerilog - Quick Reference Guide

PDF

SystemVerilog Datatypes

SystemVerilog Introduction & Logic Data Type

Video
10:50

SV Data Types - 2 State, Struct & Enum

Video
15:27

SV Data Types - Strings,Packages & Summary

Video
9:4

Knowledge Check : Data Types

Exercise

SystemVerilog Memories

SV Memories - Introduction, Packed and Multi Dimensional Arrays

Video
9:45

SV Memories - Dynamic Arrays & Queues

Video
7:41

SV Memories - Associative Arrays, Array Methods & Summary

Video
13:19

Knowledge Check:Memories

Exercise

SystemVerilog Tasks & Functions

SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task

Video
11:32

SV Tasks & Functions - Pass by value & ref and Summary

Video
9:52

Knowledge Check : Tasks & Functions

Exercise

SystemVerilog Interfaces

SV Interfaces - Introduction & Verilog ports Vs SV Interface

Video
18:44

SV Interfaces - Modports & Clocking Block

Video
18:30

SV Interfaces - Examples & Summary

Video
20:49

Knowledge Check:Interface & Clocking Block

Exercise

SystemVerilog Object Oriented Programming - Basics

SV OOP - Introduction, Class Data Type & Objects

Video
15:5

SV OOP - Constructor, Null Object, Object assignments and copy

Video
17:00

SV OOP - Shallow Vs Deep Copy & Summary

Video
17:30

Knowledge Check: Basic OOP

Exercise

SystemVerilog Object Oriented Programming - Advanced

SV OOP - Introduction, Inheritance & Super

Video
20:50

SV OOP - Static properties & methods and Pass by ref

Video
15:23

SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary

Video
21:53

Knowledge Check: Advanced OOP

Exercise

SystemVerilog Randomization

SV Randomization - Introduction, rand and randc

Video
10:58

SV Randomization - Randomize, Pre and Post randomize & Constraints

Video
12:52

SV Randomization - Set Membership, Constraints & Summary

Video
13:22

Knowledge Check: Randomization

Exercise

SystemVerilog Threads

SV Threads, Events, Mailbox and Semaphores

Video
23:11

Knowledge Check : Threads , Events, Semaphore & Mailbox

Exercise

SystemVerilog Virtual Interface

SV Virtual Interface - Introduction, Implementation & Examples

Video
17:21

Knowledge Check : Virtual Interface

Exercise

SystemVerilog Functional Coverage

SV Functional Coverage - Introduction & CRCDV

Video
15:51

SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Video
17:30

Knowledge Check : Functional Coverage

Exercise

SystemVerilog Labs

SV Labs User Guide

PDF

Lab 1 Solution : Data Types

Video
17:56

Lab 2 Solution : Interfaces

Video
9:26

Lab 3 Solution : OOP Basics

Video
8:51

Lab 4 Solution : Advanced OOP

Video
18:9

Lab 5 Solution : Randomization

Video
5:41

Lab 6 Solution : Threads, Mailbox & Semaphores

Video
22:2

Lab 7 Solution : Transaction

Video
9:43

Lab 8 Solution : Transactors

Video
9:1

Lab 9 Solution : Scoreboard & Reference Model

Video
10:59

Lab 10 Solution : Environment & Testcases

Video
11:20

SystemVerilog Lab Manual - for Synopsys VCS

PDF

SV Assignments

Assignment 1

PDF

Solution to Assignment 1

Video
15:9

Assignment 2

PDF

Solution to Assignment 2

Video
24:45

Assignment 3

PDF

Solution to Assignment 3

Video
27:41

Assignment 4

PDF

Solution to Assignment 4

Video
29:54

Assignment 5

PDF

Solution to Assignment 5

Video
9:5

Questasim - Tool Demos

Questasim- GUI and Batch Mode Usage

Video
23:10

Questasim - Coverage Report Generation

Video
10:11

Synopsys VCS and Verdi - Tool Demos

VCS- Tool Demo

Video
10:14

Verdi Tool Demo - Part-1

Video
9:16

Verdi Tool Demo - Part-2

Video
7:48

Case Study 1 : Dual Port RAM - SystemVerilog TB

Verification Plan

Video
10:18

Testbench Architecture and Verification Flow

Video
8:12

Transaction and Generator

Video
10:55

Interface and Drivers

Video
13:10

Monitors

Video
8:56

Scoreboard and Reference Model

Video
12:59

Environment and Testcases

Video
13:16

Case Study 2 : Maven SoC - SystemVerilog TB

Maven SoC SystemVerilog Verification Environment

Video
10:45

SV Mini Project

SV Mini Project (Verification of Counter RTL using SV)

PDF

Counter - TB Architecture and TB Components

Video
18:6

Feedback Form - SV,SVA Theory & Labs

Feedback Form - SV,SVA Theory & Labs

External Link

SV - Module Test

Module Test : SV & SVA

Exercise

VLSI -Verification - Design Automation Perl

2 Exercises • 10 Learning Materials

PERL Scripting

PERL Scripting - Lecture 1

Video
48:16

Knowledge check:Perl1

Exercise

PERL Scripting - Lecture 2

Video
41:35

Knowledge check: Perl2

Exercise

PERL Reference Book

PERL Reference Book

PDF

PERL Labs

Perl Labs User Guide

PDF

PERL Lab Manual

PDF

Lab 01 Solution

Video
1:34

Lab 02 Solution

Video
1:19

Lab 03 Solution

Video
1:59

Lab 04 Solution

Video
2:15

Lab 05 Solution

Video
2:47

VLSI -Verification - Assertion Based Verification-SVA

6 Exercises • 21 Learning Materials

SVA Reference Book

SVA Reference Book

PDF

SVA Introduction & Types of Assertions

What are Assertions?

Video
13:7

Necessity of using SystemVerilog Assertions

Video
14:46

Types of Assertions

Video
14:55

SVA - Knowledge Check - 1

Exercise

SVA Building Blocks, System Functions

SVA Building Blocks

Video
17:34

System Functions

Video
11:48

SVA - Knowledge Check - 2

Exercise

Writing Sequences and Implication Operators

How to write sequences?

Video
11:21

Exercise based on Implication Operators and Timing Windows

Video
14:18

Implication Operators

Video
24:34

SVA - Knowledge Check - 3

Exercise

Repetition Operators and Sequence Composition

Repetition Operators

Video
21:46

Sequence Composition

Video
19:46

Methods for Sequences

Video
7:21

SVA - Knowledge Check - 4

Exercise

Miscellaneous Concepts and Connecting Assertions to DUT

Miscllenious Cocenpts in SVA

Video
7:27

Connecting Assertions to DUT

Video
7:59

SVA - Knowledge Check - 5

Exercise

Knowledge Check : SVA

Knowledge Checks : SVA

Exercise

SVA Labs

SVA_Labs_User_Guide

PDF

SVA Lab Solution

Video
12:5

SVA Lab Manual - Synopsys VCS

PDF

SVA Case Study

Explanation to Project Specification

Video
38:5

Alarm Clock Project Specification

PDF

SVA Assignments

SVA Assignment

PDF

Solution to SVA Assignment

Video
26:9

VLSI -Verification - Universal Verification Methodology

13 Exercises • 53 Learning Materials

Universal Verification Methodology Overview

UVM_Introduction

Video
43:18

Advanced_UVM_CaseStudies

Video
48:13

Knowledge Check : Introduction to UVM

Exercise

UVM Reference Book

UVM - Quick Reference Guide

PDF

UVM TB Architecture and Base Class Hierarchy

UVM Testbench Architecture

Video
13:48

UVM Base Class Hierarchy

Video
14:31

Knowledge Check - UVM TB Architecture and Base Class Hierarchy

Exercise

UVM Factory

UVM Factory - Importance of using factory

Video
11:19

UVM Factory - Registration Process

Video
6:2

UVM Factory - Create Method and Factory Overriding

Video
11:47

Knowledge Check - UVM Factory

Exercise

UVM - Stimulus Modelling & Testbench Overview

UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Video
10:22

UVM Stimulus Modelling - Overriding the predefined do_ methods

Video
10:41

UVM - TB Overview

Video
10:44

Knowledge Check - UVM Stimulus Modelling & TB Overview

Exercise

UVM Phases & Reporting Mechanism

UVM Phases - Necessity of Phases & pre-run Phases

Video
16:27

UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Video
13:13

UVM Reporting Mechanism

Video
15:1

Knowledge Check - UVM Phases & Reporting Mechanism

Exercise

UVM TLM Ports and Configuration

UVM TLM Ports - Blocking put and get ports

Video
11:35

UVM TLM Ports - TLM FIFO and Analysis Ports

Video
13:1

UVM Configuration - Introduction to Configuration Facility

Video
13:2

UVM Configuration - Configuration class and Configuration of Virtual Interface

Video
9:31

Knowledge Check - UVM TLM Ports and Configuration

Exercise

UVM - Creating UVM Testbench Components

Creating UVM TB Components - Sequencers & Drivers

Video
15:1

Creating UVM TB Components - Monitor, Agents, Env and Testcases

Video
16:30

Knowledge Check - UVM - Creating UVM Testbench Components

Exercise

UVM Sequences

UVM Sequences - Introduction and Sequence item flow

Video
11:35

UVM Sequences - Starting the sequences and Default Sequence

Video
15:17

Knowledge Check - UVM Sequences

Exercise

UVM - Virtual Sequences & Virtual Sequencers

UVM Virtual Sequences & Virtual Sequencers - Introduction

Video
13:33

UVM Virtual Sequences & Virtual Sequencers - implementation

Video
8:22

Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

Exercise

UVM Callbacks & Events

UVM Callbacks

Video
9:23

UVM Events

Video
9:6

Knowledge Check - UVM Callbacks & Events

Exercise

UVM - Creating Scoreboard

UVM Creating Scoreboard

Video
9:20

Knowledge Check - UVM - Creating Scoreboard

Exercise

UVM - Register Abstraction Layer

UVM RAL - Intro & Definition of Register Block

Video
15:55

UVM RAL - Adapter, Predictor and Integration

Video
20:36

UVM RAL - Definition of Register Sequences

Video
11:55

Knowledge Check - UVM RAL

Exercise

UVM - CaseStudies

Advanced_UVM_CaseStudies

Video
48:13

UVM Labs

UVM Labs User Guide

PDF

Lab1 Solution : Stimulus Modeling

Video
16:2

Lab2 Solution : Factory Overriding

Video
8:19

Lab3 Solution : UVM Phases

Video
10:22

Lab4 Solution : Creating UVM agent

Video
11:44

Lab5 Solution : UVM Sequences

Video
13:22

Lab6 Solution : Virtual Interface

Video
5:50

Lab7 Solution : Agent Integration

Video
8:12

Lab8 Solution : UVM Socreboard

Video
6:39

Lab9 Solution : SoC - UVM VE implementation

Video
8:41

Lab10 Solution : Coverage & Regression

Video
4:33

UVM Lab Manual - Synopsys VCS

PDF

UVM Assignments

UVM Assignment 1

PDF

UVM Assignment 2

PDF

UVM Assignment 3

PDF

Solution to UVM Assignment 3

Video
15:39

Solution to UVM Assignment 1

Video
14:34

Solution to UVM Assignment 2

Video
15:1

Feedback Form - UVM Theory & Labs

Feedback Form - UVM Theory & Labs

External Link

UVM - Module Test

Module Test : UVM

Exercise

UVM Pilot Project (Router Verification)

Introduction

Video
7:6

Project : UVM TB Architecture

Video
15:54

Feedback Form - Router Verification Project

External Link

Practice Questions - SV & SVA

1 Exercises • 13 Learning Materials

Practice Questions - SV & SVA

Submit your solution for SV MASS question

Assignment

SV_MASS_Question - August_2024

PDF

SV_MASS_Question_July_2024

PDF

SVA_MASS_Question_June_2024

PDF

SV_MASS_Question_May_2024

PDF

SV_MASS_Question_April_2024

PDF

SV_MASS_Question_March_2024

PDF

SV_MASS_Question_January_2024

PDF

SVA_MASS_Question_November_2023

PDF

SV_MASS_Question_October_2023

PDF

SVA_MASS_Questions_August_2023

PDF

SV_ SVA_MASS_Questions_Till 2022

PDF

SVA_MASS_Question _September_2024

PDF

SV_MASS_Question _October_2024

PDF

Practice Questions - UVM

1 Exercises • 18 Learning Materials

Practice Questions - UVM

Submit your solution for UVM MASS question

Assignment

UVM_MASS_Question _August_2024

PDF

UVM_MASS_Question _July_2024

PDF

UVM_MASS_Question_June_2024

PDF

UVM_MASS_Question_May_2024

PDF

UVM_MASS_Question_April_2024

PDF

UVM_MASS_Question_March_2024

PDF

UVM_MASS_Question_February_2024

PDF

UVM_MASS_Question_December_2023

PDF

UVM_MASS_Question_September_2023

PDF

UVM_MASS_Question_July_2023

PDF

UVM_MASS_Question_June_2023

PDF

UVM_MASS_Question_May_2023

PDF

UVM_MASS_Question_April_2023

PDF

UVM_MASS_Question_March_2023

PDF

UVM_MASS_Question_February_2023

PDF

UVM_MASS_Question_January_2023

PDF

UVM_MASS_Questions_Till 2022

PDF

UVM_MASS_Question_September_2024

PDF

Frequently Asked Interview Questions- Verification

67 Learning Materials

Sample Interview Questions- SV

Sample Interview Questions - April to June 2024

PDF

Sample Interview Questions - Jan to Mar 2024

PDF

Sample Interview Questions - Oct to December 2023

PDF

Sample Interview Questions - July to September 2023

PDF

Sample Interview Questions - Apr to June 2023

PDF

Sample Interview Questions - Jan to March 2023

PDF

Sample Interview Questions - Oct to December 2022

PDF

Sample Interview Questions - Apr to June 2022

PDF

Sample Interview Questions - Jan to March 2022

PDF

Sample Interview Questions - Oct to December 2021

PDF

Sample Interview Questions - July to september 2021

PDF

Sample Interview Questions - Apr to June 2021

PDF

Sample Interview Questions - Jan to March 2021

PDF

Sample Interview Questions - Oct to December 2020

PDF

Sample Interview Questions - July to September 2020

PDF

Sample Interview Questions - Apr to June 2020

PDF

Sample Interview Questions - Jan to March 2020

PDF

Explainer Video for Interviews - SV

Interview Question 1

Video
8:51

Interview Question 2

Video
10:16

Interview Question 3

Video
7:47

Interview Question 4

Video
16:48

Interview Question 5

Video
7:14

Interview Question 6

Video
11:48

Interview Question 7

Video
20:16

Interview Question 8

Video
16:55

Sample Interview Questions- UVM

Sample Interview Questions - April to June 2024

PDF

Sample Interview Questions - Jan to Mar 2024

PDF

Sample Interview Questions - Oct to December 2023