Welcome to the Blended VLSI Verification course – a comprehensive program that strategically blends key modules, including Universal Verification Methodology (UVM), Assertion-Based Verification (SVA), and SystemVerilog Hardware Verification Language (HVL). In the UVM module, delve into essential aspects such as UVM TB Architecture, Stimulus Modeling, and Sequencing. The SVA module introduces you to assertion-based verification, covering building blocks, system functions, and practical labs. SystemVerilog HVL is a pivotal module, encompassing language concepts, object-oriented programming, and functional coverage. This course is designed to equip you with practical skills alongside theoretical knowledge, preparing you for success in the dynamic field of VLSI verification.
8 Subjects
1 Exercises • 6 Learning Materials
12 Exercises • 71 Learning Materials
2 Exercises • 10 Learning Materials
6 Exercises • 21 Learning Materials
13 Exercises • 53 Learning Materials
1 Exercises • 13 Learning Materials
1 Exercises • 18 Learning Materials
67 Learning Materials