VLSI SoC Design using Verilog HDL
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Course Overview
Course Curriculum
1 Subject
VLSI SoC Design using Verilog HDL
6 Exercises • 26 Learning Materials
VLSI Introduction
Why VLSI ?
Semiconductor Industry Overview
SoC Design
Smart Phone SoC
System On Chip Design Architecture and Methodology
ASIC Vs FPGA
ASIC Vs FPGA
VLSI Design Flow
VLSI Front-End Design Flow Part I
VLSI Front-End Design Flow Part II
VLSI Back-End Design Flow
Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Reference Material
Verilog HDL Reference Book
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
System tasks & functions
System tasks & functions
Knowledge Check - System tasks & functions
Assignments
Assignments
Knowledge Check - Assignments
Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Summary - Verilog HDL
Summary
Verilog Labs
Instructions - Verilog Labs
Verilog_lab_manual
Verilog_labs_downloadable
Solution_to_verilog_labs
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab 1
Solution to Lab 2
Solution to Lab 3
Course Instructor
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Maven Silicon
1801 Courses • 215900 Students
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