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VLSI SoC Design using Verilog HDL

Dive into VLSI System-on-Chip (SoC) design using Verilog HDL at Maven Silicon, mastering the art of designing complex systems for seamless integration and efficiency.

4.7
(6857 ratings)
Course Instructor Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview

Enroll in the VLSI SoC Design using Verilog HDL course, encompassing key modules such as VLSI Introduction, SoC Design, ASIC Vs FPGA, VLSI Design Flow, and Verilog HDL essentials. Dive into reference materials, grasp data types, Verilog operators, system tasks & functions, and engage in hands-on Verilog Labs. Elevate your understanding of structured procedures and conclude with a comprehensive summary of Verilog HDL. This course is tailored to provide you with a robust foundation in VLSI SoC Design using Verilog HDL.

Course Curriculum

1 Subject

VLSI SoC Design using Verilog HDL

6 Exercises28 Learning Materials

VLSI Introduction

Electronic System

Video
26:43

SoC Design

Smartphone - SoC - Architecture

Video
9:55

SoC Design

Video
16:59

ASIC Vs FPGA

ASIC Vs FPGA

Video
12:7

VLSI Design Flow

ASIC Design Flow - Part-1 (Specification)

Video
13:4

ASIC Design Flow - Part-2 (Architecture to RTL Design)

Video
9:32

ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)

Video
9:5

ASIC Design Flow - Part-4 (DFT to STA)

Video
10:7

ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)

Video
14:3

Introduction to Verilog HDL

Verilog_Course_Agenda

Video
14:12

VerilogHDL_Introduction

Video
28:35

Knowledge Check - Introduction to Verilog HDL

Exercise

Reference Material

Verilog HDL Reference Book

PDF

Data Types

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog Operators

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

System tasks & functions

System tasks & functions

Video
29:7

Knowledge Check - System tasks & functions

Exercise

Assignments

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Feedback Form

Feedback Form

External Link

Structured Procedures

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Summary - Verilog HDL

Summary

Video
23:58

Verilog Labs

Instructions - Verilog Labs

PDF

Verilog_lab_manual

PDF

Verilog_labs_downloadable

ZIP

Solution_to_verilog_labs

ZIP

EDA Tools - Installation Guide

Video
18:50

EDA Tools - User Guide

Video
5:22

Solution to Lab 1

Video
23:43

Solution to Lab 2

Video
6:1

Solution to Lab 3

Video
6:53

Course Instructor

tutor image

Maven Silicon

248 Courses   •   300530 Students


Ratings & Reviews

4.7 /5

6857 ratings

5451 reviews

5

69%

4

31%

3

0%

2

0%

1

0%
G
GAYATHRI.T

15 hours ago

Very clear explanation about the content.
SV
Sushmitha vavuldhas

3 days ago

AS
ALOK SAXENA

5 days ago

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