Design for Testability - DFT
Optimize your team's designs with custom training in Design for Testability (DFT) from Maven Silicon, developing strategies for building robust and testable VLSI circuits.
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Course Overview
Welcome to the Design for Testability (DFT) course, where you'll gain valuable insights into testing strategies and methodologies in the VLSI domain. This module covers Intro to Testing, Fault Collapsing, ATPG, Fault Simulation, DFT Basics, Scan Insertion & Test Compression, Boundary Scan & BIST, and various miscellaneous concepts. The Tessent Shell Overview and DFT Labs provide hands-on experiences to enhance your practical skills. The course includes a pre-assessment test to gauge your understanding before delving into the intricacies of DFT. Be prepared to explore advanced digital design concepts, Verilog HDL, and RISC-V ISA & RV32I RTL Design in subsequent modules for a holistic VLSI learning journey.
Course Instructor
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Maven Silicon
307 Courses • 396934 Students
Deepika
1 Courses • 2 Students
Paramesh Nelavalli
Kaveri
Chandana
Maven Silicon Training Support
47 Courses • 4326 Students
Ratings & Reviews
4.8 /5
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FAQs
1. What is the focus of DFT training?
2. How long does a DFT course typically last?
3. What makes a VLSI DFT course different from a regular DFT course?
4. Are DFT courses available online?
5. Can I access a DFT online course at my convenience?
6. What practical skills will I gain in a Design for Testability course?
7. Are there any online options for a Design for Testability course?
8. How is DFT online training structured?
9. What types of DFT training courses are available?
10. Can I complete DFT training entirely online?
Course Curriculum
6 Subjects
DFT - Pre Assessment
1 Exercises •
Pre Assessment Test
Pre Assessment Test : Digital
Advanced Digital Design
23 Exercises • 54 Learning Materials
Why Semiconductors?
Why Semiconductors?
Semiconductor Supply Chain
Semiconductor Supply CHain
Semiconductor Ecosystem
Semiconductor Ecosystem
AI-driven Semiconductor Industry
AI-Driven
Introduction to VLSI & SoC Design
Electronic System
Smartphone - SoC - Architecture
SoC Design
ASIC Vs FPGA
Knowledge Check : Introduction to VLSI
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
ASIC Design Flow - Part-2 (Architecture to RTL Design)
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
ASIC Design Flow - Part-4 (DFT to STA)
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Introduction To Digital Electronics
Introduction to Digital Electronics
Number System and Codes
Number Systems and Codes - Basics
Knowledge Check : Number systems-1
Number Systems
Codes
Knowledge Check : Number system and Codes-2
Logic Circuits
Logic Circuits
Knowledge Check : Logic Circuits and Boolean Algebra-1
Boolean Algebra & Logic Gates
Knowledge Check : Logic Circuits and Boolean Algebra-2
Combinational Circuits - Basics
Combinational Circuits - I
Knowledge check : Combinational Circuits Basics-1
Combinational Circuits - II
Knowledge Check : Combinational Circuits Basics-2
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Combinational Logic Circuits - Delays
Encoders, decoders and Magnitude Comparators
Knowledge Check : Combinational Circuits Advanced-1
Multiplexers and Demultiplexers
Universal Logic Gates and Tristate Buffers
Summary & Knowledge Check
Knowledge Check : Combinational Circuits Advanced -2
Sequential Circuits - Basics
Sequential Circuits - I
Knowledge Check : Sequential Circuits Basics -1
Sequential Circuits - II
Knowledge Check : Sequential Circuits Basics-2
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Flipflops - Excitation Tables and Conversion Techniques
Knowledge Check : Sequential Circuits Advanced -1
Registers & Counters
Sequence Generators & Frequency dividers
Knowledge Check : Sequential Circuits Advanced -2
Finite State Machine FSM - Basics
FSM
Knowledge Check : FSM
FSM - Advanced
Finite State Machines - Part - 1
Finite State Machines - Part - 2
Knowledge Check : Finite State Machines
Memories
Memories
Knowledge Check Memories -1
Memories & PLD
Knowledge Check : Memories, Glitches and PLD)
Static Timing Analysis - STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
Knowledge Check : Introduction to STA
STA: Clock
Clock - Part -1
Clock - Part - 2
Knowledge Check - Clock
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
Knowledge Check - Timing analysis Procedure
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
Knowledge Check - Timing analysis Procedure
STA : Techniques to Improve Timing
Different Techniques to improve timing
Knowledge Check - Techniques to Improve Timing
Feedback Form
Feedback Form
Reference Books
STA Reference Book
Advanced Digital Reference Book
Module Test : Digital & STA
Module Test : Digital & STA
Verilog HDL
13 Exercises • 43 Learning Materials
Verilog HDL Reference Material
Verilog HDL Reference Book
Verilog HDL - Quick Reference Guide
Introduction to Verilog HDL
Verilog_Course_Agenda
VerilogHDL_Introduction
Knowledge Check - Introduction to Verilog HDL
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Styles
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Compiler Directive
Compiler Directive
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Verilog Lab Manual
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
Solution to Verilog Lab 01
Solution to Verilog Lab 02
Solution to Verilog Lab 03
Solution to Verilog Lab 04
Solution to Verilog Lab 05
Solution to Verilog Lab 06
Advanced Verilog
Timescale system task & localparm
Generate block & Continuous Procedural Assignments
Self checking testbench and Automatic Tasks
Named Events and Stratified Event Queue
Knowledge Check- Advance Verilog 1
Knowledge Check- Advance Verilog 2
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
Code Coverage
Definition of Code Coverage
Condition & Expression Coverage
Statement and branch coverage
Toggle & FSM Coverage
Questasim commands for Code Coverage
Makefile for Simulations
Knowledge Check-Code Coverage 1
Code Coverage - Reference Book
Code Coverage Reference Book
Advanced Verilog & code Coverage - Labs
Advanced Verilog Lab Solutions Lab 1 & 2
Code Coverage Lab Solutions Lab 3, 4 & 5
Advanced Verilog & Code Coverage Lab Manual - Questasim
Advanced Verilog and Code Coverage Lab Manual - Synopsys VCS
Extra Reference Books
Logic Synthesis using DesignCompiler - Reference Book
Linting using VC Spyglass - Reference Book
Tcl Scripting - Reference Book
Python Scripting - Reference Book
CDC Concepts - Reference Book
Module Test : Verilog HDL
Module test : Verilog
Verilog Test
Verilog test
Design for Testability - DFT
6 Exercises • 53 Learning Materials
Reference Books
DFT Theory - Reference Book
Tessent Shell
Intro to Testing
Introduction to Testing and DFT
Verification vs Testing
Faults and Types of Testing
Levels of Testing
Fault Modelling
Knowledge check: Introduction to testing
Fault Collapsing
Fault Collapsing Part-1
Fault Collapsing Part-2
Fault Collapsing Part-3
Introduction to ATPG
Introduction to ATPG
Combinational ATPG
D-Algorithm
Fault Classes and Fault Simulation
Fault Classes
Additional Fault Models part-1
Additional Fault Models part-2
Fault Simulation
Knowledge check: Fault modelling
DFT - Basics
What is DFT?
Classification of DFT Techniques
Structured DFT Techniques
Knowledge check: DFT techniques
Scan Insertion & Test Compression
Scan Insertion Part - 1
Scan Insertion Part - 2
Scan Insertion Part - 3
Scan Insertion Part - 4
Hierachical DFT Flow
Test Compression
Knowledge check: DFT techniques
Boundary Scan & BIST
Boundary Scan
JTAG vs IJTAG
Introduction to BIST, LBIST & MBIST
Knowledge check: DFT techniques
Miscellaneous Concepts
Design Rule Checks
How to improve Test Coverage
Fault Diagnosis
Tessent Shell Overview
Intro to Tessent
System Modes
TSDB Overview
Knowledge check: Tessent shell
Feedback Form
Feedback Form
DFT - Labs
VPN Configuration Guide
DFT - Lab Manual
Solution to Lab 01
Solution to Lab 02
Solution to Lab 03
Solution to Lab 04
Solution to Lab 05
Solution to Lab 06
Solution to Lab 07
Solution to Lab 08
Solution to Lab 09
Solution to Lab 10
Solution to Lab 11
Solution to Lab 12
Solution to Lab 13
Solution to Lab 14
Solution to Lab 15
RISC-V ISA & RV32I RTL Design
1 Exercises • 24 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
Feedback Form
Feedback Form
Final Test: RISC - V design
Final Test
RISC-V Project - DFT
3 Learning Materials
RISC-V Specification
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V RV32I Quick Reference Guide
RISC-V RV32I - Quick Reference Guide for Instrcutions
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