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Advanced VLSI Design

4.5
(6 ratings)
Course Instructor Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview

Course Curriculum

5 Subjects

Design - Pre Assessment

1 Exercises

Design - Pre Assessment Test

Pre Assessment Test : Digital

Exercise

Advanced Digital Design

23 Exercises54 Learning Materials

Why Semiconductors?

Why Semiconductors?

Video
10:53

Semiconductor Supply Chain

Semiconductor Supply CHain

Video
12:31

Semiconductor Ecosystem

Semiconductor Ecosystem

Video
13:34

AI-driven Semiconductor Industry

AI-Driven

Video
7:21

Introduction to VLSI & SoC Design

Electronic System

Video
26:43

Smartphone - SoC - Architecture

Video
9:55

SoC Design

Video
16:59

ASIC Vs FPGA

Video
12:7

Knowledge Check : Introduction to VLSI

Exercise

ASIC Design Flow

ASIC Design Flow - Part-1 (Specification)

Video
13:4

ASIC Design Flow - Part-2 (Architecture to RTL Design)

Video
9:32

ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)

Video
9:5

ASIC Design Flow - Part-4 (DFT to STA)

Video
10:7

ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)

Video
14:3

Introduction To Digital Electronics

Introduction to Digital Electronics

Video
13:26

Number System and Codes

Number Systems and Codes - Basics

Video
37:45

Knowledge Check : Number systems-1

Exercise

Number Systems

Video
27:9

Codes

Video
10:9

Knowledge Check : Number system and Codes-2

Exercise

Logic Circuits

Logic Circuits

Video
55:7

Knowledge Check : Logic Circuits and Boolean Algebra-1

Exercise

Boolean Algebra & Logic Gates

Video
50:14

Knowledge Check : Logic Circuits and Boolean Algebra-2

Exercise

Combinational Circuits - Basics

Combinational Circuits - I

Video
28:25

Knowledge check : Combinational Circuits Basics-1

Exercise

Combinational Circuits - II

Video
44:8

Knowledge Check : Combinational Circuits Basics-2

Exercise

Combinational Logic Circuits - Advanced

Combinational Logic Circuits

Video
21:8

Combinational Logic Circuits - Delays

Video
9:11

Encoders, decoders and Magnitude Comparators

Video
11:41

Knowledge Check : Combinational Circuits Advanced-1

Exercise

Multiplexers and Demultiplexers

Video
18:58

Universal Logic Gates and Tristate Buffers

Video
8:37

Summary & Knowledge Check

Video
25:42

Knowledge Check : Combinational Circuits Advanced -2

Exercise

Sequential Circuits - Basics

Sequential Circuits - I

Video
40:58

Knowledge Check : Sequential Circuits Basics -1

Exercise

Sequential Circuits - II

Video
45:15

Knowledge Check : Sequential Circuits Basics-2

Exercise

Sequential Circuits - Advanced

Sequential Circuits - Latches & Flipflops

Video
25:19

Flipflops - Excitation Tables and Conversion Techniques

Video
13:16

Knowledge Check : Sequential Circuits Advanced -1

Exercise

Registers & Counters

Video
37:19

Sequence Generators & Frequency dividers

Video
26:2

Knowledge Check : Sequential Circuits Advanced -2

Exercise

Finite State Machine FSM - Basics

FSM

Video
37:39

Knowledge Check : FSM

Exercise

FSM - Advanced

Finite State Machines - Part - 1

Video
27:44

Finite State Machines - Part - 2

Video
21:43

Knowledge Check : Finite State Machines

Exercise

Memories

Memories

Video
25:54

Knowledge Check Memories -1

Exercise

Memories & PLD

Video
29:45

Knowledge Check : Memories, Glitches and PLD)

Exercise

Static Timing Analysis - STA : Introduction

Why & What is Timing Analysis?

Video
7:40

Types of Timing Analysis

Video
10:22

False Paths & Multi Cycle Paths

Video
19:36

STA in Design Flow

Video
5:24

Knowledge Check : Introduction to STA

Exercise

STA: Clock

Clock - Part -1

Video
17:35

Clock - Part - 2

Video
17:41

Knowledge Check - Clock

Exercise

STA : Timing Parameters

Timing Parameters in STA - Part-1

Video
15:49

Timing Parameters in STA - Part-2

Video
13:58

Timing Parameters in STA - Part-3

Video
10:24

Knowledge Check - Timing analysis Procedure

Exercise

STA: Timing Analysis Procedure

Timing Analysis on Sequential Circuits - Part-1

Video
18:30

Timing Analysis on Sequential Circuits - Part-2

Video
12:48

STA Procedure

Video
10:27

Knowledge Check - Timing analysis Procedure

Exercise

STA : Techniques to Improve Timing

Different Techniques to improve timing

Video
12:51

Knowledge Check - Techniques to Improve Timing

Exercise

Feedback Form

Feedback Form

External Link

Reference Books

STA Reference Book

PDF

Advanced Digital Reference Book

PDF

Module Test : Digital & STA

Module Test : Digital & STA

Exercise

Verilog HDL

12 Exercises43 Learning Materials

Verilog HDL Reference Material

Verilog HDL Reference Book

PDF

Verilog HDL - Quick Reference Guide

PDF

Introduction to Verilog HDL

Verilog_Course_Agenda

Video
14:12

VerilogHDL_Introduction

Video
28:35

Knowledge Check - Introduction to Verilog HDL

Exercise

Data Types

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog Operators

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

Verilog for Verification

Verilog for Verification

Video
29:7

Knowledge Check - Verilog for Verification

Exercise

Assignments

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Structured Proceedures

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Synthesis Coding Styles

Synthesis Coding Style

Video
20:59

Knowledge Check - Synthesis Coding Style

Exercise

Finite State Machine

Finite State Machine

Video
16:19

Knowledge Check - Finite State Machine

Exercise

Compiler Directive

Compiler Directive

Video
17:27

Summary

Verilog HDL Summary

Video
23:58

Verilog RTL Coding Examples

Video
28:40

Verilog Labs

Verilog Lab Manual

PDF

Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler

PDF

Solution to Verilog Lab 01

Video
22:2

Solution to Verilog Lab 02

Video
17:12

Solution to Verilog Lab 03

Video
11:57

Solution to Verilog Lab 04

Video
16:4

Solution to Verilog Lab 05

Video
19:10

Solution to Verilog Lab 06

Video
16:25

Advanced Verilog

Timescale system task & localparm

Video
14:48

Generate block & Continuous Procedural Assignments

Video
18:37

Self checking testbench and Automatic Tasks

Video
15:34

Named Events and Stratified Event Queue

Video
19:56

Knowledge Check- Advance Verilog 1

Exercise

Knowledge Check- Advance Verilog 2

Exercise

Advanced Verilog Reference Book

Advanced Verilog - Reference Book

PDF

Code Coverage

Definition of Code Coverage

Video
6:54

Condition & Expression Coverage

Video
7:6

Statement and branch coverage

Video
7:17

Toggle & FSM Coverage

Video
7:47

Questasim commands for Code Coverage

Video
11:26

Makefile for Simulations

Video
8:36

Knowledge Check-Code Coverage 1

Exercise

Code Coverage - Reference Book

Code Coverage Reference Book

PDF

Advanced Verilog & code Coverage - Labs

Advanced Verilog Lab Solutions Lab 1 & 2

Video
19:5

Code Coverage Lab Solutions Lab 3, 4 & 5

Video
25:16

Advanced Verilog & Code Coverage Lab Manual - Questasim

PDF

Advanced Verilog and Code Coverage Lab Manual - Synopsys VCS

PDF

Extra Reference Books

Logic Synthesis using DesignCompiler - Reference Book

PDF

Linting using VC Spyglass - Reference Book

PDF

Tcl Scripting - Reference Book

PDF

Python Scripting - Reference Book

PDF

CDC Concepts - Reference Book

PDF

Module Test : Verilog HDL

Module test : Verilog

Exercise

RISC-V ISA & RV32I RTL Design

1 Exercises24 Learning Materials

RISC-V Instruction Set Architecture

RISC-V Overview

Video
9:42

RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)

Video
12:17

RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)

Video
9:15

RISC-V ISA Part-1 ( introduction)

Video
10:43

RISC-V ISA Part-2 ( RISC-V Registers and Modes)

Video
15:58

RISC-V ISA Part-3 ( introduction to Privileged Architecture)

Video
20:42

Base ISA

Video
15:6

RV32I Base Instructions(R & I type)

Video
23:9

RV32I Base Instructions(S & B Type)

Video
23:30

RV32I Base Instructions(J Type)

Video
15:19

RV32I Base Instructions (U type)

Video
17:11

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

RISC-V RV32I Reference Guide

RISC-V RV32I Quick Reference Guide

PDF

Feedback Form

Feedback Form

External Link

Final Test: RISC - V design

RISC-V design

Exercise

RISC-V Project - DD

3 Learning Materials

RISC-V RV32I Quick Reference Guide

RISC-V RV32I - Quick Reference Guide for Instrcutions

PDF

RISC-V Specification

The RISC-V Instruction Set Manual

PDF

MSRV32I Core Design Specification

PDF

Course Instructor

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Maven Silicon

248 Courses   •   300529 Students


Ratings & Reviews

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