Advanced ASIC Verification
Tailor your team's ASIC verification skills with Maven Silicon's custom training, focusing on advanced methodologies for robust digital designs.
4.8
(24 ratings)
Course Instructors
Maven Silicon
Deepika
Paramesh Nelavalli
Kaveri
Chandana
Maven Silicon Training Support
To enroll in this course, please contact the Admin
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Course Overview
Welcome to the Advanced ASIC Verification course tailored for corporates. This specialized program delves into crucial aspects of verification methodologies, equipping professionals with advanced skills. Explore SystemVerilog, UVM, SVA, and engage in practical case studies covering dual-port RAM and Maven SoC. Additionally, gain expertise in RISC-V ISA, RTL design, and VLSI SoC Design. This course is designed to meet the unique needs of corporate teams, ensuring a comprehensive and practical understanding of advanced ASIC verification techniques.
Course Curriculum
6 Subjects
Verification - Pre Assessment
1 Exercises •
Pre Assessment Test
Pre Assessment Test
Exercise
VLSI SoC Design
1 Exercises • 9 Learning Materials
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Advanced ASIC Verification
29 Exercises • 118 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Verification Methodologies & Summary
Video
00:27:11
Constraint Random Coverage Driven Verification
Video
00:25:37
Knowledge Check : Verification Methodology Overview
Exercise
SystemVerilog Language Concepts
SV Concepts Agenda
Video
00:06:38
SV Overview
Video
00:11:16
SV Randomization & Functional Coverage
Video
00:06:47
SV TB Architecture
Video
00:10:19
SV Interface
Video
00:14:51
SV Virtual Interface
Video
00:11:40
SV OOP
Video
00:13:56
SV Transactions
Video
00:14:46
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
00:10:50
SV Data Types - 2 State, Struct & Enum
Video
00:15:27
SV Data Types - Strings,Packages & Summary
Video
00:09:04
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
00:09:45
SV Memories - Dynamic Arrays & Queues
Video
00:07:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
00:13:19
Knowledge Check:Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
00:11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
00:09:52
Knowledge Check : Tasks & Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
00:18:44
SV Interfaces - Modports & Clocking Block
Video
00:18:30
SV Interfaces - Examples & Summary
Video
00:20:49
Knowledge Check:Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
00:15:05
SV OOP - Constructor, Null Object, Object assignments and copy
Video
00:17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
00:17:30
Knowledge Check: Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
00:20:50
SV OOP - Static properties & methods and Pass by ref
Video
00:15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
00:21:53
Knowledge Check: Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
00:10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
00:12:52
SV Randomization - Set Membership, Constraints & Summary
Video
00:13:22
Knowledge Check: Randomization
Exercise
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Video
00:23:11
Knowledge Check : Threads , Events, Semaphore & Mailbox
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
00:17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
00:15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
00:17:30
Knowledge Check : Functional Coverage
Exercise
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Video
00:10:18
Testbench Architecture and Verification Flow
Video
00:08:12
Transaction and Generator
Video
00:10:55
Interface and Drivers
Video
00:13:10
Monitors
Video
00:08:56
Scoreboard and Reference Model
Video
00:12:59
Environment and Testcases
Video
00:13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
00:10:45
SystemVerilog Labs
SystemVerilog Lab Manual
PDF
Lab 1 Solution : Data Types
Video
00:17:56
Lab 2 Solution : Interfaces
Video
00:09:26
Lab 3 Solution : OOP Basics
Video
00:08:51
Lab 4 Solution : Advanced OOP
Video
00:18:09
Lab 5 Solution : Randomization
Video
00:05:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
00:22:02
Lab 7 Solution : Transaction
Video
00:09:43
Lab 8 Solution : Transactors
Video
00:09:01
Lab 9 Solution : Scoreboard & Reference Model
Video
00:10:59
Lab 10 Solution : Environment & Testcases
Video
00:11:20
SVA Introduction & Types of Assertions
What are Assertions?
Video
00:13:07
Necessity of using SystemVerilog Assertions
Video
00:14:46
Types of Assertions
Video
00:14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks, System Functions
SVA Building Blocks
Video
00:17:34
System Functions
Video
00:11:48
SVA - Knowledge Check - 2
Exercise
Writing Sequences and Implication Operators
How to write sequences?
Video
00:11:21
Implication Operators
Video
00:24:34
Exercise based on Implication Operators and Timing Windows
Video
00:14:18
SVA - Knowledge Check - 3
Exercise
Repetition Operators and Sequence Composition
Repetition Operators
Video
00:21:46
Sequence Composition
Video
00:19:46
Methods for Sequences
Video
00:07:21
SVA - Knowledge Check - 4
Exercise
Miscellaneous Concepts and Connecting Assertions to DUT
Miscellaneous Concepts in SVA
Video
00:07:27
Connecting Assertions to DUT
Video
00:07:59
SVA - Knowledge Check - 5
Exercise
SVA Labs
SVA Labs User Guide
PDF
SVA Lab Solution
Video
00:12:05
SVA Lab Manual
PDF
SVA Reference Book
SVA Reference Book
PDF
Universal Verification Methodology Overview
UVM_Introduction
Video
00:43:18
Advanced_UVM_CaseStudies
Video
00:48:13
Knowledge Check : Introduction to UVM
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
00:13:48
UVM Base Class Hierarchy
Video
00:14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
00:11:19
UVM Factory - Registration Process
Video
00:06:02
UVM Factory - Create Method and Factory Overriding
Video
00:11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
00:10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
00:10:41
UVM - TB Overview
Video
00:10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
00:16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
00:13:13
UVM Reporting Mechanism
Video
00:15:01
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
00:11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
00:13:01
UVM Configuration - Introduction to Configuration Facility
Video
00:13:02
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
00:09:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
00:15:01
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
00:16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
00:11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
00:15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
00:13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
00:08:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
Feedback Form
Feedback Form
External Link
UVM Callbacks & Events
UVM Callbacks
Video
00:09:23
UVM Events
Video
00:09:06
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
00:09:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM Labs
UVM Lab Manual
PDF
Lab1 Solution : Stimulus Modeling
Video
00:16:02
Lab2 Solution : Factory Overriding
Video
00:08:19
Lab3 Solution : UVM Phases
Video
00:10:22
Lab4 Solution : Creating UVM agent
Video
00:11:44
Lab5 Solution : UVM Sequences
Video
00:13:22
Lab6 Solution : Virtual Interface
Video
00:05:50
Lab7 Solution : Agent Integration
Video
00:08:12
Lab8 Solution : UVM Scoreboard
Video
00:06:39
Lab9 Solution : SoC - UVM VE implementation
Video
00:08:41
Lab10 Solution : Coverage & Regression
Video
00:04:33
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
00:15:55
UVM RAL - Adapter, Predictor and Integration
Video
00:20:36
UVM RAL - Definition of Register Sequences
Video
00:11:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
00:48:13
RISC-V ISA & RV32I RTL Design
1 Exercises • 24 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
00:09:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
Feedback Form
Feedback Form
External Link
Final Test: RISC - V design
Final Test
Exercise
RISC-V Project - DV
4 Learning Materials
RISC-V RV32I Quick reference Guides
RISC-V RV32I reference Card for V-Plan
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
RISC-V Specification
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
DV-Final Test-Corporate
1 Exercises •
Final Test
Final Test
Exercise
Course Instructor
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Maven Silicon
307 Courses • 397004 Students
Deepika
1 Courses • 2 Students
Paramesh Nelavalli
Kaveri
Chandana
Maven Silicon Training Support
47 Courses • 4326 Students
Ratings & Reviews
4.8 /5
24 ratings
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FAQs
1. What is ASIC verification and why is it important?
ASIC verification is a critical process in ensuring that the design of Application-Specific Integrated Circuits (ASICs) functions correctly and meets its specifications before manufacturing. It helps detect errors and potential failures early in the design phase.
2. What is involved in the ASIC design process?
ASIC design involves defining the circuit's functionality, creating a logical design, performing simulations, and generating the final layout for fabrication. It includes tasks such as RTL coding, synthesis, placement, routing, and verification.
3. How does VLSI verification relate to ASIC design?
VLSI verification ensures that very large scale integration (VLSI) designs, including ASICs, are correct and meet the required functionality. It includes simulation, model checking, and formal verification to find bugs and validate the design.
4. What is the ASIC design flow?
The ASIC design flow consists of various stages, including specification, RTL design, synthesis, placement, routing, and verification. This flow ensures that the design meets the required performance, area, and power constraints.
5. What is the difference between ASIC and FPGA?
An ASIC (Application-Specific Integrated Circuit) is custom-designed for a particular use, offering higher performance but at a higher cost and longer development time. FPGA (Field-Programmable Gate Array) is reconfigurable and offers flexibility, but may not achieve the same level of performance as ASICs.
6. How is the ASIC design flow applied in VLSI?
In VLSI, the ASIC design flow is applied in stages, starting from design specification and moving through RTL design, verification, synthesis, placement, and routing, all aimed at creating an optimized chip for production.
7. What does the term ASIC flow refer to in chip design?
ASIC flow refers to the sequence of steps involved in designing an ASIC, including logic design, verification, synthesis, place and route, and post-silicon testing, ensuring that the design is functional and manufacturable.
8. What role does ASIC flow play in VLSI design?
In VLSI, ASIC flow plays a central role in ensuring that the designed circuit meets performance, area, and power specifications, involving stages such as design entry, verification, synthesis, and physical design.
9. How do ASICs compare to FPGAs in terms of performance?
ASICs generally offer superior performance in terms of speed, power efficiency, and area optimization when compared to FPGAs, but they come with a longer design cycle and higher costs, whereas FPGAs are more flexible and faster to deploy.
10. What is the importance of ASIC in VLSI design?
ASICs play a key role in VLSI design by offering customized solutions for specific applications, enabling higher performance and lower power consumption compared to general-purpose processors. They are essential in modern VLSI-based systems.
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