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Advanced ASIC Verification

Tailor your team's ASIC verification skills with Maven Silicon's custom training, focusing on advanced methodologies for robust digital designs.

4.7
(16 ratings)
Course Instructor Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview

Welcome to the Advanced ASIC Verification course tailored for corporates. This specialized program delves into crucial aspects of verification methodologies, equipping professionals with advanced skills. Explore SystemVerilog, UVM, SVA, and engage in practical case studies covering dual-port RAM and Maven SoC. Additionally, gain expertise in RISC-V ISA, RTL design, and VLSI SoC Design. This course is designed to meet the unique needs of corporate teams, ensuring a comprehensive and practical understanding of advanced ASIC verification techniques.

Course Curriculum

6 Subjects

Verification - Pre Assessment

1 Exercises

Pre Assessment Test

Pre Assessment Test

Exercise

VLSI SoC Design

1 Exercises9 Learning Materials

Introduction to VLSI & SoC Design

Electronic System

Video
26:43

Smartphone - SoC - Architecture

Video
9:55

SoC Design

Video
16:59

ASIC Vs FPGA

Video
12:7

Knowledge Check : Introduction to VLSI

Exercise

ASIC Design Flow

ASIC Design Flow - Part-1 (Specification)

Video
13:4

ASIC Design Flow - Part-2 (Architecture to RTL Design)

Video
9:32

ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)

Video
9:5

ASIC Design Flow - Part-4 (DFT to STA)

Video
10:7

ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)

Video
14:3

Advanced ASIC Verification

29 Exercises118 Learning Materials

Verification Methodology Overview

Introduction to Verification Methodology

Video
22:25

Verification Process

Video
21:46

Reusable TB

Video
7:24

Verification Environment Architecture

Video
19:2

Verification Methodologies & Summary

Video
27:11

Constraint Random Coverage Driven Verification

Video
25:37

Knowledge Check : Verification Methodology Overview

Exercise

SystemVerilog Language Concepts

SV Concepts Agenda

Video
6:38

SV Overview

Video
11:16

SV Randomization & Functional Coverage

Video
6:47

SV TB Architecture

Video
10:19

SV Interface

Video
14:51

SV Virtual Interface

Video
11:40

SV OOP

Video
13:56

SV Transactions

Video
14:46

Knowledge Check : SV language Concepts Overview

Exercise

SystemVerilog Reference Book

SystemVerilog - Quick Reference Guide

PDF

SystemVerilog Datatypes

SystemVerilog Introduction & Logic Data Type

Video
10:50

SV Data Types - 2 State, Struct & Enum

Video
15:27

SV Data Types - Strings,Packages & Summary

Video
9:4

Knowledge Check : Data Types

Exercise

SystemVerilog Memories

SV Memories - Introduction, Packed and Multi Dimensional Arrays

Video
9:45

SV Memories - Dynamic Arrays & Queues

Video
7:41

SV Memories - Associative Arrays, Array Methods & Summary

Video
13:19

Knowledge Check:Memories

Exercise

SystemVerilog Tasks & Functions

SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task

Video
11:32

SV Tasks & Functions - Pass by value & ref and Summary

Video
9:52

Knowledge Check : Tasks & Functions

Exercise

SystemVerilog Interfaces

SV Interfaces - Introduction & Verilog ports Vs SV Interface

Video
18:44

SV Interfaces - Modports & Clocking Block

Video
18:30

SV Interfaces - Examples & Summary

Video
20:49

Knowledge Check:Interface & Clocking Block

Exercise

SystemVerilog Object Oriented Programming - Basics

SV OOP - Introduction, Class Data Type & Objects

Video
15:5

SV OOP - Constructor, Null Object, Object assignments and copy

Video
17:00

SV OOP - Shallow Vs Deep Copy & Summary

Video
17:30

Knowledge Check: Basic OOP

Exercise

SystemVerilog Object Oriented Programming - Advanced

SV OOP - Introduction, Inheritance & Super

Video
20:50

SV OOP - Static properties & methods and Pass by ref

Video
15:23

SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary

Video
21:53

Knowledge Check: Advanced OOP

Exercise

SystemVerilog Randomization

SV Randomization - Introduction, rand and randc

Video
10:58

SV Randomization - Randomize, Pre and Post randomize & Constraints

Video
12:52

SV Randomization - Set Membership, Constraints & Summary

Video
13:22

Knowledge Check: Randomization

Exercise

SystemVerilog Threads, Mailboxes and Semaphores

SV Threads , Events, Mailbox and Semaphores

Video
23:11

Knowledge Check : Threads , Events, Semaphore & Mailbox

Exercise

SystemVerilog Virtual Interface

SV Virtual Interface - Introduction, Implementation & Examples

Video
17:21

Knowledge Check : Virtual Interface

Exercise

SystemVerilog Functional Coverage

SV Functional Coverage - Introduction & CRCDV

Video
15:51

SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Video
17:30

Knowledge Check : Functional Coverage

Exercise

Case Study 1 : Dual Port RAM - SystemVerilog TB

Verification Plan

Video
10:18

Testbench Architecture and Verification Flow

Video
8:12

Transaction and Generator

Video
10:55

Interface and Drivers

Video
13:10

Monitors

Video
8:56

Scoreboard and Reference Model

Video
12:59

Environment and Testcases

Video
13:16

Case Study 2 : Maven SoC - SystemVerilog TB

Maven SoC SystemVerilog Verification Environment

Video
10:45

SystemVerilog Labs

SystemVerilog Lab Manual

PDF

Lab 1 Solution : Data Types

Video
17:56

Lab 2 Solution : Interfaces

Video
9:26

Lab 3 Solution : OOP Basics

Video
8:51

Lab 4 Solution : Advanced OOP

Video
18:9

Lab 5 Solution : Randomization

Video
5:41

Lab 6 Solution : Threads, Mailbox & Semaphores

Video
22:2

Lab 7 Solution : Transaction

Video
9:43

Lab 8 Solution : Transactors

Video
9:1

Lab 9 Solution : Scoreboard & Reference Model

Video
10:59

Lab 10 Solution : Environment & Testcases

Video
11:20

SVA Introduction & Types of Assertions

What are Assertions?

Video
13:7

Necessity of using SystemVerilog Assertions

Video
14:46

Types of Assertions

Video
14:55

SVA - Knowledge Check - 1

Exercise

SVA Building Blocks, System Functions

SVA Building Blocks

Video
17:34

System Functions

Video
11:48

SVA - Knowledge Check - 2

Exercise

Writing Sequences and Implication Operators

How to write sequences?

Video
11:21

Implication Operators

Video
24:34

Exercise based on Implication Operators and Timing Windows

Video
14:18

SVA - Knowledge Check - 3

Exercise

Repetition Operators and Sequence Composition

Repetition Operators

Video
21:46

Sequence Composition

Video
19:46

Methods for Sequences

Video
7:21

SVA - Knowledge Check - 4

Exercise

Miscellaneous Concepts and Connecting Assertions to DUT

Miscellaneous Concepts in SVA

Video
7:27

Connecting Assertions to DUT

Video
7:59

SVA - Knowledge Check - 5

Exercise

SVA Labs

SVA Labs User Guide

PDF

SVA Lab Solution

Video
12:5

SVA Lab Manual

PDF

SVA Reference Book

SVA Reference Book

PDF

Universal Verification Methodology Overview

UVM_Introduction

Video
43:18

Advanced_UVM_CaseStudies

Video
48:13

Knowledge Check : Introduction to UVM

Exercise

UVM Reference Book

UVM - Quick Reference Guide

PDF

UVM TB Architecture and Base Class Hierarchy

UVM Testbench Architecture

Video
13:48

UVM Base Class Hierarchy

Video
14:31

Knowledge Check - UVM TB Architecture and Base Class Hierarchy

Exercise

UVM Factory

UVM Factory - Importance of using factory

Video
11:19

UVM Factory - Registration Process

Video
6:2

UVM Factory - Create Method and Factory Overriding

Video
11:47

Knowledge Check - UVM Factory

Exercise

UVM - Stimulus Modelling & Testbench Overview

UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Video
10:22

UVM Stimulus Modelling - Overriding the predefined do_ methods

Video
10:41

UVM - TB Overview

Video
10:44

Knowledge Check - UVM Stimulus Modelling & TB Overview

Exercise

UVM Phases & Reporting Mechanism

UVM Phases - Necessity of Phases & pre-run Phases

Video
16:27

UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Video
13:13

UVM Reporting Mechanism

Video
15:1

Knowledge Check - UVM Phases & Reporting Mechanism

Exercise

UVM TLM Ports and Configuration

UVM TLM Ports - Blocking put and get ports

Video
11:35

UVM TLM Ports - TLM FIFO and Analysis Ports

Video
13:1

UVM Configuration - Introduction to Configuration Facility

Video
13:2

UVM Configuration - Configuration class and Configuration of Virtual Interface

Video
9:31

Knowledge Check - UVM TLM Ports and Configuration

Exercise

UVM - Creating UVM Testbench Components

Creating UVM TB Components - Sequencers & Drivers

Video
15:1

Creating UVM TB Components - Monitor, Agents, Env and Testcases

Video
16:30

Knowledge Check - UVM - Creating UVM Testbench Components

Exercise

UVM Sequences

UVM Sequences - Introduction and Sequence item flow

Video
11:35

UVM Sequences - Starting the sequences and Default Sequence

Video
15:17

Knowledge Check - UVM Sequences

Exercise

UVM - Virtual Sequences & Virtual Sequencers

UVM Virtual Sequences & Virtual Sequencers - Introduction

Video
13:33

UVM Virtual Sequences & Virtual Sequencers - implementation

Video
8:22

Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

Exercise

Feedback Form

Feedback Form

External Link

UVM Callbacks & Events

UVM Callbacks

Video
9:23

UVM Events

Video
9:6

Knowledge Check - UVM Callbacks & Events

Exercise

UVM - Creating Scoreboard

UVM Creating Scoreboard

Video
9:20

Knowledge Check - UVM - Creating Scoreboard

Exercise

UVM Labs

UVM Lab Manual

PDF

Lab1 Solution : Stimulus Modeling

Video
16:2

Lab2 Solution : Factory Overriding

Video
8:19

Lab3 Solution : UVM Phases

Video
10:22

Lab4 Solution : Creating UVM agent

Video
11:44

Lab5 Solution : UVM Sequences

Video
13:22

Lab6 Solution : Virtual Interface

Video
5:50

Lab7 Solution : Agent Integration

Video
8:12

Lab8 Solution : UVM Scoreboard

Video
6:39

Lab9 Solution : SoC - UVM VE implementation

Video
8:41

Lab10 Solution : Coverage & Regression

Video
4:33

UVM - Register Abstraction Layer

UVM RAL - Intro & Definition of Register Block

Video
15:55

UVM RAL - Adapter, Predictor and Integration

Video
20:36

UVM RAL - Definition of Register Sequences

Video
11:55

Knowledge Check - UVM RAL

Exercise

UVM - CaseStudies

Advanced_UVM_CaseStudies

Video
48:13

RISC-V ISA & RV32I RTL Design

1 Exercises24 Learning Materials

RISC-V Instruction Set Architecture

RISC-V Overview

Video
9:42

RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)

Video
12:17

RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)

Video
9:15

RISC-V ISA Part-1 ( introduction)

Video
10:43

RISC-V ISA Part-2 ( RISC-V Registers and Modes)

Video
15:58

RISC-V ISA Part-3 ( introduction to Privileged Architecture)

Video
20:42

Base ISA

Video
15:6

RV32I Base Instructions(R & I type)

Video
23:9

RV32I Base Instructions(S & B Type)

Video
23:30

RV32I Base Instructions(J Type)

Video
15:19

RV32I Base Instructions (U type)

Video
17:11

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

RISC-V RV32I Reference Guide

RISC-V RV32I Quick Reference Guide

PDF

Feedback Form

Feedback Form

External Link

Final Test: RISC - V design

RISC-V design

Exercise

RISC-V Project - DV

4 Learning Materials

RISC-V RV32I Quick reference Guides

RISC-V RV32I reference Card for V-Plan

PDF

RISC-V RV32I - Quick Reference Guide for Instrcutions

PDF

RISC-V Specification

The RISC-V Instruction Set Manual

PDF

MSRV32I Core Design Specification

PDF

DV-Final Test

1 Exercises

DV - Final test

Final test

Exercise

Course Instructor

tutor image

Maven Silicon

252 Courses   •   311099 Students


Ratings & Reviews

4.7 /5

16 ratings

3 reviews

5

69%

4

31%

3

0%

2

0%

1

0%
MK
Manoj Kumar Sevilla

a month ago

LC
Lalit Chaudhari

2 months ago

A comprehensive course which is well structured and good hands on examples.
JS
Jeet Shah

3 months ago

Some code snippets in the answer could have been presented in a visually better way.

FAQs

1. What is ASIC verification and why is it important?

ASIC verification is a critical process in ensuring that the design of Application-Specific Integrated Circuits (ASICs) functions correctly and meets its specifications before manufacturing. It helps detect errors and potential failures early in the design phase.

2. What is involved in the ASIC design process?

ASIC design involves defining the circuit's functionality, creating a logical design, performing simulations, and generating the final layout for fabrication. It includes tasks such as RTL coding, synthesis, placement, routing, and verification.

3. How does VLSI verification relate to ASIC design?

VLSI verification ensures that very large scale integration (VLSI) designs, including ASICs, are correct and meet the required functionality. It includes simulation, model checking, and formal verification to find bugs and validate the design.

4. What is the ASIC design flow?

The ASIC design flow consists of various stages, including specification, RTL design, synthesis, placement, routing, and verification. This flow ensures that the design meets the required performance, area, and power constraints.

5. What is the difference between ASIC and FPGA?

An ASIC (Application-Specific Integrated Circuit) is custom-designed for a particular use, offering higher performance but at a higher cost and longer development time. FPGA (Field-Programmable Gate Array) is reconfigurable and offers flexibility, but may not achieve the same level of performance as ASICs.

6. How is the ASIC design flow applied in VLSI?

In VLSI, the ASIC design flow is applied in stages, starting from design specification and moving through RTL design, verification, synthesis, placement, and routing, all aimed at creating an optimized chip for production.

7. What does the term ASIC flow refer to in chip design?

ASIC flow refers to the sequence of steps involved in designing an ASIC, including logic design, verification, synthesis, place and route, and post-silicon testing, ensuring that the design is functional and manufacturable.

8. What role does ASIC flow play in VLSI design?

In VLSI, ASIC flow plays a central role in ensuring that the designed circuit meets performance, area, and power specifications, involving stages such as design entry, verification, synthesis, and physical design.

9. How do ASICs compare to FPGAs in terms of performance?

ASICs generally offer superior performance in terms of speed, power efficiency, and area optimization when compared to FPGAs, but they come with a longer design cycle and higher costs, whereas FPGAs are more flexible and faster to deploy.

10. What is the importance of ASIC in VLSI design?

ASICs play a key role in VLSI design by offering customized solutions for specific applications, enabling higher performance and lower power consumption compared to general-purpose processors. They are essential in modern VLSI-based systems.

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