RISC-V RV32I RTL Design

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This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions. In this course, you will explore how you can create a processor using all the basic building blocks like register, memory, adder, multiplexer, ALU, decoder and control logic like FSMs.

Also, it explains why CPU performance is very essential and how to improve CPU performance through a pipeline design methodology. In this course, you will explore how to implement a five-stage pipelined RISC-V processor.

Prerequisite: Any electronics/electrical engineering graduate with good knowledge in Digital Electronics, RISC-V ISA and basic RISC-V RV32I assembly programming.

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Curriculum

1: RISC-V RV32I Reference Guide
Lecture 1 RISC-V RV32I Quick Reference Guide 5 Pages

2: RISC-V RV32I RTL Architecture Design
Lecture 2 RISC-V Execution Stages and Flow 08:36
Lecture 3 RISC-V Register File and RV32I Instructions Format 12:52
Lecture 4 RV32I – R Type ALU Datapath 09:29
Lecture 5 RV32I – I Type ALU Datapath 06:33
Lecture 6 RV32I – S Type ALU Datapath - Load & Store 13:03
Lecture 7 RV32I – B Type ALU Datapath 08:22
Lecture 8 RV32I – J Type ALU Datapath – JAL & JALR 09:25
Lecture 9 RV32I – U Type ALU Datapath and Summary 10:18
Quiz 1 Knowledge Check - RISC-V RTL Architecture Design 8 Questions

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Course Price
Discount	- $ 178
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Total	$ 178