This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions. In this course, you will explore how you can create a processor using all the basic building blocks like register, memory, adder, multiplexer, ALU, decoder and control logic like FSMs.
Also, it explains why CPU performance is very essential and how to improve CPU performance through a pipeline design methodology. In this course, you will explore how to implement a five-stage pipelined RISC-V processor.
Prerequisite: Any electronics/electrical engineering graduate with good knowledge in Digital Electronics, RISC-V ISA and basic RISC-V RV32I assembly programming.Read full details
1: RISC-V RV32I Reference Guide
2: RISC-V RV32I RTL Architecture Design