Advanced Physical Design and Verification
Explore Maven Silicon's Advanced Physical Design and Verification course to elevate expertise in both physical design and verification with advanced techniques and real-world applications.
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Course Overview
Embark on an advanced journey through the intricacies of Physical Design and Verification with this comprehensive course. Master Verilog HDL, CMOS design, Synthesis, DFT, and STA, followed by in-depth exploration of tools like Primetime and Fusion Compiler. Dive into critical aspects of Floorplanning, Placement, CTS, Routing, and Physical Verification, concluding with a hands-on RISC-V PD Implementation project.
Course Curriculum
21 Subjects
Must Reads
2 Learning Materials
Onboarding & Platform Details
Must Knows - Very Important
PDF
Admission Form
Admission Form
External Link
Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:44
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:08
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:06
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Linux Operating System
1 Exercises • 7 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
Video
01:15:00
vi Text Editor
Video
00:31:00
Knowledge check: Linux
Exercise
Labs User Guide & VPN Configuration Guide
Ubuntu Installation Guide
PDF
Linux Labs User Guide
PDF
Linux Lab Manual
PDF
Linux Lab 1 : Solution
Video
00:08:26
Linux Lab 2 : Solution
Video
00:05:15
Verilog - HDL
8 Exercises • 24 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Verilog_Course_Agenda
Video
00:14:13
VerilogHDL_Introduction
Video
00:28:36
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Advanced Verilog for Verification
Advance Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Summary
Video
00:23:58
Feedback Form
Feedback form
feedback_form
Verilog Labs
Instructions - Verilog Labs
PDF
Verilog Lab Manual
PDF
Verilog Labs Folder - Download
ZIP
EDA Tools - Installation Guide
Video
00:18:50
EDA Tools - User Guide
Video
00:05:22
Solution to Lab 1
Video
00:23:39
Solution to Lab 2
Video
00:10:25
Solution to Lab 3
Video
00:05:58
Solution to Lab 4
Video
00:06:51
Solution to Lab 5
Video
00:06:37
Solution to Lab 6
Video
00:08:14
Solutions - Verilog Labs - Download
ZIP
VLSI - Physical Design : CMOS Design and Technologies
24 Learning Materials
Introduction to CMOS
CMOS : An Introduction to CMOS
Video
00:15:39
CMOS : MOS Fundamentals - Part 1
Video
00:15:59
CMOS : MOS Fundamentals - Part 2
Video
00:20:22
CMOS : MOS Fundamentals - Part 3
Video
00:11:39
Reference Materials : CMOS
PDF
CMOS - MOS Characteristics
CMOS : MOS - IV Characteristics : Part 1
Video
00:16:06
CMOS : MOS - IV Characteristics : Part 2
Video
00:07:16
CMOS : MOS - IV Characteristics : Part 3
Video
00:13:35
CMOS - Various Designs
CMOS : Inverter Design - Part 1
Video
00:15:30
CMOS : Inverter Design - Part 2
Video
00:21:40
CMOS : Inverter Design - Part 3
Video
00:14:33
CMOS : Combinational Circuits - Part 1
Video
00:13:27
CMOS : Combinational Circuits - Part 2
Video
00:16:22
CMOS : Logical Effort
Video
00:20:33
CMOS Layout and Stick Diagrams
CMOS : Layout Design - Part 1
Video
00:15:55
CMOS : Layout Design - Part 2
Video
00:07:53
CMOS : Stick Diagrams
Video
00:21:34
CMOS : Alternatives to CMOS
CMOS : Alternatives to CMOS - Part 1
Video
00:13:01
CMOS : Alternatives to CMOS - Part 2
Video
00:15:34
CMOS : Alternatives to CMOS - Part 3
Video
00:16:32
CMOS Labs
PD_Tanner_Tool_video_1
Video
00:20:59
PD_Tannner_Tool_Video_2
Video
00:38:11
PD_Tanner_Tool_Video_3
Video
00:27:24
Tanner Tool Lab Manual
PDF
VLSI - Physical Design : Synthesis and PDKs
2 Exercises • 20 Learning Materials
Libraries and PDKs
Libraries and PDKs- Part 1
Video
00:18:38
Libraries and PDKs - Part 2
Video
00:10:25
Synthesis
Synthesis Concepts
Video
00:16:07
Synthesis Steps
Video
00:14:30
Synthesis Varients
Video
00:10:02
Libraries, Synthesis and PDKs : Reference Material
Synthesis : Reference Material
PDF
Libraries and PDKs : Reference Material
PDF
SDC : Reference Material
PDF
Synopsys Design Compiler ( SDC )
SDC Fundamentals
Video
00:08:45
Object Access Commands
Video
00:11:50
Understanding SDC - Break down sections and System Interfaces
Video
00:03:20
Set Driving Cells and Set Load Commands
Video
00:03:09
Clock Types - Timing Constraints and Design Rule Constraints
Video
00:08:39
Commands to create different types of clocks
Video
00:05:26
Defining Input and Output delays
Video
00:15:27
Clock Domain Crossing and Timing Exceptions
Video
00:09:16
Maximum Delay and Power Optimization Commands
Video
00:11:18
Knowledge Check : Synthesis and PDKs
Exercise
Feedback Form - PD
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
Module Test 1: Intro to PD, CMOS , Synthesis & PDK and DFT
Module Test : Intro to PD, CMOS , Synthesis & PDK andDFT
Exercise
Introduction to Physical Design
1 Exercises • 10 Learning Materials
Introduction to Physical Design
Introduction to VLSI Design
Video
00:06:19
Design Styles
Video
00:09:36
Partitioning
Video
00:05:12
Floorplanning
Video
00:05:34
Placement
Video
00:05:34
Clock Tree Synthesis [ CTS ]
Video
00:06:35
Routing
Video
00:04:21
Static Timing Analysis [ STA ]
Video
00:05:24
Knowledge Check : Introduction to PD
Exercise
Reference Book : Introduction to Physical Design
Introduction to Physical Design
PDF
Advanced_Physical_Design_Verification
PDF
Design for Testability
1 Exercises • 20 Learning Materials
DFT Theory
Introduction to DFT
Video
00:11:15
Types of Testing
Video
00:08:24
Basic Testing Principles
Video
00:11:39
Fault Collapsing
Video
00:12:27
What is DFT?
Video
00:10:50
DFT Techniques - Ad-hoc Techniques
Video
00:10:15
DFT Techniques- Structured Techniques
Video
00:09:15
BIST & boundary Scan
Video
00:12:08
Introduction to BIST, LBIST & MBIST
Video
00:19:59
Knowledge check: DFT
Exercise
DFT Reference Book
DFT Reference Book
PDF
Tessent Shell - Introduction
Introduction to Tessent Shell
Video
00:03:37
System Modes
Video
00:03:13
TSDB
Video
00:05:23
DFT lab Solutions
Lab 01 : MBIST
Video
00:16:16
Lab 02 : DRC
Video
00:16:56
Lab 03 : Boundary Scan
Video
00:08:49
Lab 04 : Scan Chain
Video
00:09:23
Lab 05 : IJTAG
Video
00:16:40
Lab 06 : EDT
Video
00:10:06
DFT Lab Manual
PDF
Static Timing Analysis (PD)
2 Exercises • 18 Learning Materials
Timing Analysis, STA, DTA , False path and Multicycle Path
Timing Analysis, STA, DTA, FalsePath, Multicycle Path
Video
02:07:29
STA in Digital Design Flow, Inputs and Outputs of STA Tools
Video
00:40:53
Clocks , Different Types of clocks, Uncertainties with the Clock
Clocks , Different Types of Clocks, Uncertainties With the Clock
Video
01:22:59
Timing Parameters In STA
Timing Parameters In STA
Video
00:54:09
Recovery and Removal Times and PVT Corners and their effect on Cell Delays
Video
01:49:58
Setup and Hold Times
Setup and Hold Times
Video
01:20:54
Setup and Hold In Equality Equations
Video
01:21:11
What is Prime Time
What is PrimeTime
Video
01:57:07
PrimeTime Lab Manual
Video
00:06:31
OCV and CRPR
OCV and CRPR
Video
01:23:41
Modelling of CMOS Logic Cells
Modelling of CMOS Logic Cells
Video
01:16:30
Different Techniques to improve timing
Different Techniques to improve timing
Video
01:51:11
Knowledge Check : STA
Exercise
STA : Reference Material
STA: Reference Material
PDF
STA Assignment
STA Assignment 1
PDF
STA Assignment 2
PDF
Feedback form
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
Module Test 2 : STA, SDC, Primetime
Module Test 2 : STA, SDC, Primetime
Exercise
Primetime - Tool Demo and Lab Solutions
1 Exercises • 43 Learning Materials
Reference Material
STA Labs Refernce Material
PDF
Primetime Tool Demo
Introduction to Primetime Tool
Video
00:07:04
STA Process
Video
00:04:59
PrimeTime in the implementation flow
Video
00:07:37
Timing Analysis Flow in PrimeTime
Video
00:04:18
How to read and interpret the timing reports (Part-1)
Video
00:04:39
How to read and interpret the timing reports (Part-2)
Video
00:11:39
How to invoke PrimeTime and use it?
Video
00:09:06
How to setup PT Tool with various inputs?
Video
00:08:37
How to write tcl scripts to automate loading the inputs and report generation?
Video
00:05:27
How to run various reporting commands?
Video
00:10:30
How to use GUI and understand histogram?
Video
00:05:20
STA Lab Manual
PrimeTime Lab Manual
PDF
Primetime : Lab 01
Task_1_Restore_a_Prime_Time_Session
Video
00:09:45
Task_2_ Explore_some_helpful_commands
Video
00:07:00
Task_3_Validate_an_Existing_Prime_Time_Session
Video
00:08:37
Task_4_ Execute_the_Run_Script_and_Analyze_the_run
Video
00:08:15
Task_5_Analyze_STA_Reports
Video
00:10:48
Primetime : Lab 02
Task_1_validate_constraints
Video
00:07:39
Task_2_Analyse_Timing_Report_for_Input_Delay_Constraint
Video
00:10:11
Task_3_Analyse_Timing_Report_for_Output_Delay_Constraint
Video
00:07:08
Primetime : Lab 03
Task_1_Setup_PrimeTime_for_Lab3
Video
00:03:51
Task_2_Generate_Summary_Reports
Video
00:12:27
Task_3_Analyse_Timing_Reports_for_Setup_and_Hold
Video
00:12:36
Task_4_ Apply_the_Correct_Timing_Report_Switches
Video
00:08:04
Task_5_Identify_Half-Clock_Cycle_Paths
Video
00:06:50
Primetime : Lab 04
Task 1 - Get to Know the Design Clocks
Video
00:14:01
Task 2 - Use the GUI to Report Clock Relationships
Video
00:18:11
Task 3 - Use the GUI to explore detail of timing paths
Video
00:11:15
Task 4 - Report a false violations
Video
00:10:00
Task 5 - Re-execute the run script to reduce violations
Video
00:03:10
Primetime : Lab 05
Lab5 - Task1
Video
00:09:19
Lab5 - Task2
Video
00:16:04
Primetime : Lab 06
Lab 06 : Task 1
Video
00:03:44
Lab 06 : Task 2
Video
00:03:32
Lab 06 : Task 3
Video
00:05:49
Lab 06 : Task 4
Video
00:03:56
Primetime : Lab 07
Lab 07 : Task 1
Video
00:04:15
Lab 07 : Task 2
Video
00:15:35
Lab 07 : Task 3
Video
00:02:44
Primetime : Lab 08
Lab 08 : Task 1
Video
00:08:21
Lab 08 : Task 2
Video
00:11:28
Lab 08 : Task 3
Video
00:03:07
Knowledge Check : Primetime
Knowledge Checks : Primetime
Exercise
VLSI - Physical Design : Floor Planning and Power Planning
2 Exercises • 9 Learning Materials
Floor Planning
Introduction to Floor Planning
Video
00:15:19
Floor Planning : Aspect Ratio Utilization
Video
00:15:09
Floor Planning : Macros
Video
00:17:30
Floor Planning : Blockages
Video
00:13:20
Knowledge Check : Floor planning
Exercise
Power Planning
Introduction to Power Planning
Video
00:14:32
Power Planning : Regions, Patterns, Extensions
Video
00:08:55
Power Planning : Mesh Pattern
Video
00:16:38
Power Planning : Strageic Connection
Video
00:21:46
Power planning : PNA
Video
00:05:22
Knowledge Check : Power planning
Exercise
VLSI - Physical Design : Placement
1 Exercises • 20 Learning Materials
Placement
Placement : An Introduction
Video
00:04:42
Goals of Placement
Video
00:13:12
Placement : Cost Components and flow
Video
00:15:13
Detailed Placement
Video
00:02:45
Congestion and Overflow
Video
00:21:05
Timing driven placement and strategies
Video
00:14:43
HFNS and Cloning
Video
00:09:59
Scan Chain Reordering
Video
00:07:58
Placement Qualification and Outputs
Video
00:07:41
Knowledge Check : Placement
Exercise
Placement Flow Overview
PDF
Fusion Compiler : Lab 07
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:42
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:58
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:53
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:58
VLSI - Physical Design : Signal Integrity and Cross Talk
8 Learning Materials
Signal Integrity and Crosstalk
Introduction to SI and CT
Video
00:07:53
Reasons for Signal Integrity and Crosstalk
Video
00:13:52
Impact of Lateral and Interlayer Capacitance
Video
00:13:31
Understanding the Noise Margin
Video
00:15:54
Crosstalk Effects
Video
00:06:00
Crosstalk Mechanisms
Video
00:07:15
Noise Protection Techniques for SI and CT
Video
00:12:32
Signal Integrity and Crosstalk : Reference Material
Signal Integrity and Crosstalk : Reference Material
PDF
VLSI - Physical Design : Clock Tree Synthesis
5 Learning Materials
Clock Tree Synthesis
Clock Tree Synthesis - An Introduction
Video
00:09:52
Pre CTS
Video
00:18:26
CTS : What is clock
Video
00:07:04
CTS Cell Selection
Video
00:18:26
Clock Tree Synthesis : Reference Material
CTS : Reference Material
PDF
VLSI - Physical Design : Routing
2 Exercises • 7 Learning Materials
Routing
Routing : An Introduction
Video
00:14:55
Routing : Global Routing
Video
00:25:38
Routing : Detail Routing
Video
00:17:13
Knowledge Check: Routing
Exercise
Routing : Reference Material
Routing : Reference Material
PDF
Feedback form
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
Module Test 3: Floorplanning, Powerplanning, Placement, CTS, Routing
Module test 3: Floorplanning, Powerplan, Placement, CTS, Routing
Exercise
VLSI - Physical Design : Physical Verification
2 Exercises • 22 Learning Materials
Physical Verification : An Introduction
Physical Verification : Introduction
Video
00:10:05
Physical Verification : DRC
Video
00:12:24
Physical Verification : LVS
Video
00:08:56
Physical Verification : PERC - Part 1
Video
00:11:42
Physical Verification : PERC - Part 2
Video
00:15:22
Physical Verification : PERC - Part 3
Video
00:22:13
Physical Verification : PERC - Part 4
Video
00:13:14
Physical Verification : PERC - Part 5
Video
00:14:09
Knowledge Check - Physical Verification
Exercise
Physical Verification : Reference Material
Physical Verification : DRC & LVS - Reference Material
PDF
Physical verification : Calibre PERC - Reference Material
PDF
Physical Verification Labs
Physical Verification Using Calibre Tool - Lab Manual
PDF
Introduction to Calibre GUI
Video
01:06:07
Calibre - Lab 1
Video
00:32:48
Calibre - lab 2
Video
00:23:04
Calibre - Lab 3 & 4
Video
00:18:13
Calibre Tool Demo - Physical Verification
Video
00:05:30
Calibre Tool Demo - Design Rules
Video
00:12:56
Calibre Tool Demo - Calibre DRC Flow
Video
00:05:04
Calibre Tool Demo - Solving DRC using Calibre nmdrc tool
Video
00:05:27
Calibre Tool Demo - Layout Versus Schematic
Video
00:06:01
Calibre Tool Demo -Calibre nmlvs Flow
Video
00:11:46
Feedback Form - PD Theory & Labs
Feedback Form - PD Theory & Labs
External Link
Module test 4 : SI & CT, Signoff, ECO and Physical Verification
Module test 4 : SI & CT, Signoff, ECO and Physical Verification
Exercise
VLSI - Physical Design - Fusion Compiler ( Design Implementation) : Tool Demo and Labs
1 Exercises • 35 Learning Materials
Introduction to Design Implementation
Fusion Compiler : Design Implementation
Video
00:05:30
Fusion Compiler : Lab 07
Fusion Compiler : Design Implementation - Lab 07 - Task 1
Video
00:03:42
Fusion Compiler : Design Implementation - Lab 07 - Task 2
Video
00:09:48
Fusion Compiler : Design Implementation - Lab 07 - Task 3
Video
00:02:25
Fusion Compiler : Design Implementation - Lab 07 - Task 4
Video
00:06:30
Fusion Compiler : Design Implementation - Lab 07 - Task 5
Video
00:07:53
Fusion Compiler : Design Implementation - Lab 07 - Task 6
Video
00:09:57
Fusion Compiler : Design Implementation - Lab 07 - Task 8
Video
00:06:58
Fusion Compiler : Design Implementation - Lab 07 - Task 7
Video
00:06:39
Fusion Compiler : Design Implementation - Lab 07 - Task 9
Video
00:03:53
Fusion Compiler : Design Implementation - Lab 07 - Task 10
Video
00:18:58
Fusion Compiler : Lab 08
Fusion Compiler : Design Implementation - Lab 08A : Task 1
Video
00:12:26
Fusion Compiler : Design Implementation - Lab 08A : Task 2
Video
00:23:02
Fusion Compiler : Design Implementation - Lab 08A - Task 3
Video
00:14:29
Fusion Compiler : Design Implementation - Lab 08A - Task 4
Video
00:10:16
Fusion Compiler : Design Implementation - Lab 08A - Task 5
Video
00:13:17
Fusion Compiler : Design Implementation - Lab 08B - Task 1
Video
00:23:25
Fusion Compiler : Design Implementation - Lab 08B - Task 2
Video
00:07:20
Fusion Compiler : Design Implementation - Lab 08B - Task 3
Video
00:03:02
Fusion Compiler : Design Implementation - Lab 08B - Task 4
Video
00:09:51
Fusion Compiler : Design Implementation - Lab 08B - Task 5
Video
00:21:56
Fusion Compiler : Design Implementation - Lab 08B - Task 6
Video
00:17:32
Fusion Compiler : Design Implementation - Lab 08B - Task 8
Video
00:11:37
Fusion Compiler : Lab 09
Fusion Compiler : Design Implementation - Lab 09 - Task 1
Video
00:06:15
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 1
Video
00:20:51
Fusion Compiler : Design Implementation - Lab 09 - Task 2 - Part 2
Video
00:14:25
Fusion Compiler : Lab 10 - Sign off
Signoff
Video
00:05:49
ECO Flow
Video
00:03:07
ECO Flow In Fusion Compiler
Video
00:00:36
Timing ECOs
Video
00:02:24
Spare Cells
Video
00:00:53
Manual ECO Vs Automated ECOs
Video
00:02:12
ECO Fusion Work Flow
Video
00:04:16
Signoff_ECO_Flow
PDF
Knowledge Check : Signoff / ECO
Exercise
Fusion Compiler : Lab 10 - Task 1 & 2
Video
00:22:45
VLSI - Physical Design - Fusion Compiler (Design Planning) : Tool Demo and Labs
50 Learning Materials
Introduction to Fusion Compiler
Fusion Compiler : Compile Flow
Video
00:14:52
Physical Design Using Fusion Compiler Lab Manual
Fusion Compiler Lab Manual
PDF
Fusion Compiler : Lab 01
Fusion Compiler : Introduction
Video
00:21:46
Fusion Compiler: Design Planning - Lab 01 : Task 02
Video
00:03:04
Fusion Compiler : Design Planning - Lab 01 : Task 03
Video
00:09:31
Fusion Compiler : Design Planning - Lab 01 : Task 04 to Task 06
Video
00:05:53
Fusion Compiler : Design Planning - Lab 01 : Task 07
Video
00:05:33
Fusion Compiler : Design Planning - Lab 01 : Task 08
Video
00:04:34
Fusion Compiler : Design Planning - Lab 01 : Task 09
Video
00:09:03
Fusion Compiler : Design Planning - Lab 01 : Task 10 & Task 11
Video
00:12:24
Fusion Compiler : Lab 02
Fusion Compiler : Design Creation ( Reading RTL)
Video
00:19:23
Fusion Compiler : DMM
Video
00:10:09
Fusion Compiler : Design Planning - Lab 02 : Task 01
Video
00:05:31
Fusion Compiler : Design Planning - Lab 02 : Task 02
Video
00:22:49
Fusion Compiler : Design Planning - Lab 02 : Task 03
Video
00:10:26
Fusion Compiler : Design Planning - Lab 02 : Task 04
Video
00:07:33
Fusion Compiler : Lab 03
Compile_Flow
Video
00:14:52
Fusion Compiler : Design Planning - Lab 03 : Task 1
Video
00:03:57
Fusion Compiler : Design Planning - Lab 03 : Task 2
Video
00:06:08
DFT_Flow
Video
00:03:15
Fusion Compiler : Design Planning - Lab 03 : Task 3
Video
00:07:12
Fusion Compiler : Design Planning - Lab 03 : Task 4
Video
00:05:16
Fusion Compiler : Design Planning - Lab 03 : Task 5
Video
00:10:21
Fusion Compiler : Design Planning - Lab 03 : Task 6
Video
00:17:15
Fusion Compiler : Design Planning - Lab 03 : Task 7
Video
00:14:08
Fusion Compiler : Design Planning - Lab 03 : Task 8
Video
00:07:26
Fusion Compiler : Lab 04
Fusion Compiler : Design Planning - Lab 04 : Task 5
Video
00:19:08
Technology Setup
Video
00:17:02
Fusion Compiler : Design Planning - Lab 04 : Task 1
Video
00:05:33
Fusion Compiler : Design Planning - Lab 04 : Task 2
Video
00:08:36
Fusion Compiler : Design Planning - Lab 04 : Task 3
Video
00:05:52
Auto_Floorplan
Video
00:19:06
Fusion Compiler : Design Planning - Lab 04 : Task 4
Video
00:07:33
MCMMM - Part 1
Video
00:29:51
MCMMM - Part 2
Video
00:18:45
Fusion Compiler : Lab 05
CCD - Part 1
Video
00:21:03
CCD - Part 2
Video
00:07:09
CCD - part 3
Video
00:18:17
Fusion Compiler : Design Planning - Lab 05 : Task 1
Video
00:13:18
Fusion Compiler : Design Planning - Lab 05 : Task 2
Video
00:11:19
Fusion Compiler : Design Planning - Lab 05 : Task 3
Video
00:15:21
Fusion Compiler : Design Planning - Lab 05 : Task 4
Video
00:07:38
Fusion Compiler : Lab 06
ICGs - Part 1
Video
00:17:06
ICGs - Part 2
Video
00:18:21
ICGs - Part 3
Video
00:07:05
ICGs - Part 4
Video
00:16:33
ICGs - Part 5
Video
00:12:38
Fusion Compiler : Design Planning - Lab 06 : Task 1
Video
00:25:10
Fusion Compiler : Design Planning - Lab 06 : Task 2
Video
00:15:46
Fusion Compiler : Design Planning - Lab 06 : Task 3
Video
00:09:23
RISC-V PD Implementation - Project
10 Learning Materials
Router Mini Project PD Implementation Using Fusion Compiler
Router - Physical Design Implementation Using Fusion Compiler
PDF
RISC-V Design Specification
RISC- V IP Physical Design Implementation Using DC and ICC2
PDF
RISC-V QRG
PDF
RISC-V Implementation Using DC ICCII Flow
Video
00:03:32
Synthesis tcl script
Video
00:05:48
Synthesis Using DC - Running Script and Viewing Schematic
Video
00:02:24
Analysing area timing and Power reports
Video
00:02:01
Design setup and Floorplanning
Video
00:09:31
Power Planning
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00:04:07
Placement_CTS_Routing
Video
00:07:30
VLSI - Physical Design - Tcl
1 Exercises • 14 Learning Materials
Introduction to Tcl
Introduction to Tcl-1
PDF
Introduction to TCL-2
PDF
Introduction to Tcl
Video
00:15:29
Control Flow Statements
Video
00:26:26
Procedures
Video
00:17:05
Feedback form
feedback_form
Data types - Strings
Video
00:15:16
Mathematical Operators
Video
00:14:00
Datatypes - Lists
Video
00:19:45
Data types - Arrays
Video
00:11:38
Data types - Dictionaries
Video
00:10:23
Practice Applications
Video
00:11:47
Tcl : Knowledge Check
Exercise
Tcl Manual
Tcl manual
PDF
Feedback Form - Overall Experience
Feedback form
feedback_form
Interview Preparation
2 Learning Materials
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
00:50:11
Create a winning LinkedIn Profile
How to create a winning LinkedIn profile?
Video
00:37:57
Course Instructor
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FAQs
1. What is covered in a VLSI physical design process?
The VLSI physical design process includes floorplanning, placement, routing, and timing optimization, ensuring the chip meets design constraints.
2. Why is physical verification important in VLSI design?
Physical verification ensures the design adheres to manufacturing rules and performs as expected, minimizing errors in the final chip.
3. What will you learn in a VLSI physical design course?
A VLSI physical design course covers concepts like floorplanning, placement, routing, and DRC/LVS checks, with hands-on tools like Cadence and Synopsys.
4. Is a physical design course helpful for beginners in VLSI?
Yes, a physical design course introduces key concepts and tools, building a strong foundation for a career in semiconductor design.
5. What does PD flow in VLSI consist of?
PD flow in VLSI includes stages like partitioning, floorplanning, power planning, placement, routing, and verification for silicon implementation.
6. How is physical design flow in VLSI structured?
Physical design flow in VLSI involves sequential steps: design import, floorplanning, placement, clock tree synthesis, routing, and verification.
7. What are the main checks in physical verification in VLSI?
Physical verification in VLSI involves DRC (Design Rule Check) and LVS (Layout Versus Schematic) to ensure design manufacturability and functionality.
8. What tools are commonly used in VLSI physical design?
Tools like Cadence Innovus, Synopsys ICC2, and Mentor Graphics Olympus are widely used for implementing VLSI physical design processes effectively.
9. What challenges are addressed by physical verification?
Physical verification addresses challenges like layout errors, electrical rule violations, and ensuring compliance with foundry design rules for chip manufacturability.
10. Who can benefit from enrolling in a VLSI physical design course?
Students, freshers, and working professionals aiming to specialize in chip implementation and physical design can greatly benefit from a VLSI physical design course.
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