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Design for Testability - DFT

4.8
(74 ratings)
Course Instructor Maven Silicon
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Course Overview

Course Curriculum

6 Subjects

DFT - Pre Assessment

1 Exercises 0 Learning Materials

Pre Assessment Test

Pre Assessment Test : Digital

Exercise

Advanced Digital Design

23 Exercises 45 Learning Materials

VLSI SoC Design

Why SoC?

Video
17:12

Mobile SoC Architecture

Video
9:35

SoC Design Process

Video
19:00

Moores Law, ASIC Vs FPGA

Video
15:10

VLSI Design Flow

Video
35:32

Knowledge Check : Introduction to VLSI

Exercise

Introduction To Digital Electronics

Introduction to Digital Electronics

Video
13:26

Number System and Codes

Number Systems and Codes - Basics

Video
37:45

Knowledge Check : Number systems-1

Exercise

Number Systems

Video
27:9

Codes

Video
10:9

Knowledge Check : Number system and Codes-2

Exercise

Logic Circuits

Logic Circuits

Video
55:7

Knowledge Check : Logic Circuits and Boolean Algebra-1

Exercise

Boolean Algebra & Logic Gates

Video
50:14

Knowledge Check : Logic Circuits and Boolean Algebra-2

Exercise

Combinational Circuits - Basics

Combinational Circuits - I

Video
28:25

Knowledge check : Combinational Circuits Basics-1

Exercise

Combinational Circuits - II

Video
44:8

Knowledge Check : Combinational Circuits Basics-2

Exercise

Combinational Logic Circuits - Advanced

Combinational Logic Circuits

Video
21:8

Combinational Logic Circuits - Delays

Video
9:11

Encoders, decoders and Magnitude Comparators

Video
11:41

Knowledge Check : Combinational Circuits Advanced-1

Exercise

Multiplexers and Demultiplexers

Video
18:58

Universal Logic Gates and Tristate Buffers

Video
8:37

Summary & Knowledge Check

Video
25:42

Knowledge Check : Combinational Circuits Advanced -2

Exercise

Sequential Circuits - Basics

Sequential Circuits - I

Video
40:58

Knowledge Check : Sequential Circuits Basics -1

Exercise

Sequential Circuits - II

Video
45:15

Knowledge Check : Sequential Circuits Basics-2

Exercise

Sequential Circuits - Advanced

Sequential Circuits - Latches & Flipflops

Video
25:19

Flipflops - Excitation Tables and Conversion Techniques

Video
13:16

Knowledge Check : Sequential Circuits Advanced -1

Exercise

Registers & Counters

Video
37:19

Sequence Generators & Frequency dividers

Video
26:2

Knowledge Check : Sequential Circuits Advanced -2

Exercise

Finite State Machine FSM - Basics

FSM

Video
37:39

Knowledge Check : FSM

Exercise

FSM - Advanced

Finite State Machines - Part - 1

Video
27:44

Finite State Machines - Part - 2

Video
21:43

Knowledge Check : Finite State Machines

Exercise

Memories

Memories

Video
25:54

Knowledge Check Memories -1

Exercise

Memories & PLD

Video
29:45

Knowledge Check : Memories, Glitches and PLD)

Exercise

Static Timing Analysis - STA : Introduction

Why & What is Timing Analysis?

Video
7:40

Types of Timing Analysis

Video
10:22

False Paths & Multi Cycle Paths

Video
19:36

STA in Design Flow

Video
5:24

Knowledge Check : Introduction to STA

Exercise

STA: Clock

Clock - Part -1

Video
17:35

Clock - Part - 2

Video
17:41

Knowledge Check - Clock

Exercise

STA : Timing Parameters

Timing Parameters in STA - Part-1

Video
15:49

Timing Parameters in STA - Part-2

Video
13:58

Timing Parameters in STA - Part-3

Video
10:24

Knowledge Check - Timing analysis Procedure

Exercise

STA: Timing Analysis Procedure

Timing Analysis on Sequential Circuits - Part-1

Video
18:30

Timing Analysis on Sequential Circuits - Part-2

Video
12:48

STA Procedure

Video
10:27

Knowledge Check - Timing analysis Procedure

Exercise

STA : Techniques to Improve Timing

Different Techniques to improve timing

Video
12:51

Knowledge Check - Techniques to Improve Timing

Exercise

Reference Books

STA Reference Book

PDF

Advanced Digital Reference Book

PDF

Module Test : Digital & STA

Module Test : Digital & STA

Exercise

Verilog HDL

12 Exercises 43 Learning Materials

Introduction to Verilog HDL

Setting Expectations - Course Agenda

Video
12:1

Introduction to Verilog HDL

Video
23:59

Knowledge Check - Introduction to Verilog HDL

Exercise

Verilog HDL Reference Material

Verilog HDL Reference Book

PDF

Verilog HDL - Quick Reference Guide

PDF

Data Types

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog Operators

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

Verilog for Verification

Verilog for Verification

Video
29:7

Knowledge Check - Verilog for Verification

Exercise

Assignments

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Structured Proceedures

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Synthesis Coding Styles

Synthesis Coding Style

Video
20:59

Knowledge Check - Synthesis Coding Style

Exercise

Finite State Machine

Finite State Machine

Video
16:19

Knowledge Check - Finite State Machine

Exercise

Compiler Directive

Compiler Directive

Video
17:27

Summary

Verilog HDL Summary

Video
23:58

Verilog RTL Coding Examples

Video
28:40

Verilog Labs

Verilog Lab Manual

PDF

Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler

PDF

Solution to Verilog Lab 01

Video
22:2

Solution to Verilog Lab 02

Video
17:12

Solution to Verilog Lab 03

Video
11:57

Solution to Verilog Lab 04

Video
16:4

Solution to Verilog Lab 05

Video
19:10

Solution to Verilog Lab 06

Video
16:25

Advanced Verilog

Timescale system task & localparm

Video
14:48

Generate block & Continuous Procedural Assignments

Video
18:37

Self checking testbench and Automatic Tasks

Video
15:34

Named Events and Stratified Event Queue

Video
19:56

Knowledge Check- Advance Verilog 1

Exercise

Knowledge Check- Advance Verilog 2

Exercise

Advanced Verilog Reference Book

Advanced Verilog - Reference Book

PDF

Code Coverage

Definition of Code Coverage

Video
6:54

Condition & Expression Coverage

Video
7:6

Statement and branch coverage

Video
7:17

Toggle & FSM Coverage

Video
7:47

Questasim commands for Code Coverage

Video
11:26

Makefile for Simulations

Video
8:36

Knowledge Check-Code Coverage 1

Exercise

Code Coverage - Reference Book

Code Coverage Reference Book

PDF

Advanced Verilog & code Coverage - Labs

Advanced Verilog Lab Solutions Lab 1 & 2

Video
19:5

Code Coverage Lab Solutions Lab 3, 4 & 5

Video
25:16

Advanced Verilog & Code Coverage Lab Manual - Questasim

PDF

Advanced Verilog and Code Coverage Lab Manual - Synopsys VCS

PDF

Extra Reference Books

Logic Synthesis using DesignCompiler - Reference Book

PDF

Linting using VC Spyglass - Reference Book

PDF

Tcl Scripting - Reference Book

PDF

Python Scripting - Reference Book

PDF

CDC Concepts - Reference Book

PDF

Module Test : Verilog HDL

Module test : Verilog

Exercise

Design for Testability - DFT

6 Exercises 51 Learning Materials

Reference Books

DFT Theory - Reference Book

PDF

Tessent Shell

PDF

Intro to Testing

Introduction to Testing and DFT

Video
12:51

Verification vs Testing

Video
3:12

Faults and Types of Testing

Video
7:40

Levels of Testing

Video
5:52

Fault Modelling

Video
11:38

Knowledge check: Introduction to testing

Exercise

Fault Collapsing

Fault Collapsing Part-1

Video
7:23

Fault Collapsing Part-2

Video
5:20

Fault Collapsing Part-3

Video
5:24

Introduction to ATPG

Introduction to ATPG

Video
4:56

Combinational ATPG

Video
5:20

D-Algorithm

Video
7:13

Fault Classes and Fault Simulation

Fault Classes

Video
14:45

Additional Fault Models part-1

Video
11:46

Additional Fault Models part-2

Video
8:2

Fault Simulation

Video
10:34

Knowledge check: Fault modelling

Exercise

DFT - Basics

What is DFT?

Video
9:50

Classification of DFT Techniques

Video
7:38

Structured DFT Techniques

Video
3:25

Knowledge check: DFT techniques

Exercise

Scan Insertion & Test Compression

Scan Insertion Part - 1

Video
7:17

Scan Insertion Part - 2

Video
3:4

Scan Insertion Part - 3

Video
4:44

Scan Insertion Part - 4

Video
5:38

Hierachical DFT Flow

Video
7:25

Test Compression

Video
14:51

Knowledge check: DFT techniques

Exercise

Boundary Scan & BIST

Boundary Scan

Video
33:00

JTAG vs IJTAG

Video
10:5

Introduction to BIST, LBIST & MBIST

Video
19:59

Knowledge check: DFT techniques

Exercise

Miscellaneous Concepts

Design Rule Checks

Video
3:4

How to improve Test Coverage

Video
4:21

Fault Diagnosis

Video
2:38

Tessent Shell Overview

Intro to Tessent

Video
3:37

System Modes

Video
3:13

TSDB Overview

Video
5:23

Knowledge check: Tessent shell

Exercise

DFT - Labs

DFT - Lab Manual

PDF

Solution to Lab 01

Video
10:32

Solution to Lab 02

Video
4:56

Solution to Lab 03

Video
5:12

Solution to Lab 04

Video
4:20

Solution to Lab 05

Video
2:22

Solution to Lab 06

Video
7:15

Solution to Lab 07

Video
6:49

Solution to Lab 08

Video
4:2

Solution to Lab 09

Video
8:23

Solution to Lab 10

Video
5:29

Solution to Lab 11

Video
5:23

Solution to Lab 12

Video
3:4

Solution to Lab 13

Video
9:57

Solution to Lab 14

Video
12:30

Solution to Lab 15

Video
7:25

RISC-V ISA & RV32I RTL Design

1 Exercises 20 Learning Materials

RISC-V Instruction Set Architecture

Why RISC-V Processor?

Video
6:50

RISC-V processor overview

Video
10:24

RISC-V ISA Overview

Video
12:13

RV32I R Type Instruction

Video
9:29

RV32I I Type Instruction

Video
7:47

RV32I S and B Type Instructions

Video
11:55

RV32I J and U Type Instructions

Video
12:35

RV32I Assembly Programs and Summary

Video
19:22

Knowloedge Check : RISC-V ISA

Exercise

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

RISC-V RV32I Reference Guide

RISC-V RV32I Quick Reference Guide

PDF

RISC-V Project - DFT

0 Exercises 3 Learning Materials

RISC-V Specification

The RISC-V Instruction Set Manual

PDF

MSRV32I Core Design Specification

PDF

RISC-V RV32I Quick Reference Guide

RISC-V RV32I - Quick Reference Guide for Instrcutions

PDF

Course Instructor

tutor image

Maven Silicon

1608 Courses   •   177129 Students


Ratings & Reviews

4.8 /5

76 ratings

74 reviews

5

77%

4

23%

3

0%

2

0%

1

0%
S
Susmitha

5 months ago

NN
NANDINI N

8 months ago

the course covers all the basic concepts dft . well structured
ST
SHUBHASHREE T

8 months ago

Good learning experience

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