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Verilog HDL

4.7
(239 ratings)
Course Instructor Sivakumar P R
To purchase this course, please contact the admin
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Course Overview

Course Curriculum

1 Subject

Verilog HDL

12 Exercises 43 Learning Materials

Introduction to Verilog HDL

Setting Expectations - Course Agenda

Video
12:1

Introduction to Verilog HDL

Video
23:59

Knowledge Check - Introduction to Verilog HDL

Exercise

Verilog HDL Reference Material

Verilog HDL Reference Book

PDF

Verilog HDL - Quick Reference Guide

PDF

Data Types

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog Operators

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

Verilog for Verification

Verilog for Verification

Video
29:7

Knowledge Check - Verilog for Verification

Exercise

Assignments

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Structured Proceedures

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Synthesis Coding Styles

Synthesis Coding Style

Video
20:59

Knowledge Check - Synthesis Coding Style

Exercise

Finite State Machine

Finite State Machine

Video
16:19

Knowledge Check - Finite State Machine

Exercise

Compiler Directive

Compiler Directive

Video
17:27

Summary

Verilog HDL Summary

Video
23:58

Verilog RTL Coding Examples

Video
28:40

Verilog Labs

Verilog Lab Manual

PDF

Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler

PDF

Solution to Verilog Lab 01

Video
22:2

Solution to Verilog Lab 02

Video
17:12

Solution to Verilog Lab 03

Video
11:57

Solution to Verilog Lab 04

Video
16:4

Solution to Verilog Lab 05

Video
19:10

Solution to Verilog Lab 06

Video
16:25

Advanced Verilog

Timescale system task & localparm

Video
14:48

Generate block & Continuous Procedural Assignments

Video
18:37

Self checking testbench and Automatic Tasks

Video
15:34

Named Events and Stratified Event Queue

Video
19:56

Knowledge Check- Advance Verilog 1

Exercise

Knowledge Check- Advance Verilog 2

Exercise

Advanced Verilog Reference Book

Advanced Verilog - Reference Book

PDF

Code Coverage

Definition of Code Coverage

Video
6:54

Condition & Expression Coverage

Video
7:6

Statement and branch coverage

Video
7:17

Toggle & FSM Coverage

Video
7:47

Questasim commands for Code Coverage

Video
11:26

Makefile for Simulations

Video
8:36

Knowledge Check-Code Coverage 1

Exercise

Code Coverage - Reference Book

Code Coverage Reference Book

PDF

Advanced Verilog & code Coverage - Labs

Advanced Verilog Lab Solutions Lab 1 & 2

Video
19:5

Code Coverage Lab Solutions Lab 3, 4 & 5

Video
25:16

Advanced Verilog & Code Coverage Lab Manual - Questasim

PDF

Advanced Verilog and Code Coverage Lab Manual - Synopsys VCS

PDF

Extra Reference Books

Logic Synthesis using DesignCompiler - Reference Book

PDF

Linting using VC Spyglass - Reference Book

PDF

Tcl Scripting - Reference Book

PDF

Python Scripting - Reference Book

PDF

CDC Concepts - Reference Book

PDF

Module Test : Verilog HDL

Module test : Verilog

Exercise

Course Instructor

tutor image

Sivakumar P R

17 Courses   •   1935 Students

CEO and Founder, Maven Silicon

Ratings & Reviews

4.7 /5

253 ratings

239 reviews

5

76%

4

24%

3

0%

2

0%

1

0%
S
Susmitha

5 months ago

MJ
Milan Jauhari

8 months ago

GOOD
ST
Sabiha Tanveez

8 months ago

it was really helpful

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