This Assertion Based Verification [ SVA ] hands-on course explains the concept of Assertion Based Verification [ ABV ] using SystemVerilog assertions [ SVA ] and how one can verify the DUT protocol or functionality using the same. As part of the course, we will walk you through all the concepts like immediate and concurrent assertions, sequences, implication & repetition operators, writing complex assertions using sequences, etc. and guide you to do all the necessary labs to understand the same.
We use assertions primarily to verify the DUT protocol and functionality. Also, assertions are very powerful in debugging the simulation failures efficiently and verifying the DUT functionality through formal verification technologies too. As assertions are highly reusable from block level to SoC level verification, we verification engineers use ABV extensively to verify the modules, IPs, Sub-Systems, Chips, and SoCs in the semiconductor industry.
Any electronics engineer with a good knowledge of RTL design using Verilog HDL can learn the ABV using SVA without having any exposure/knowledge in the SystemVerilog language. This is one of the best ways for engineers to begin their verification journey with SystemVerilog .
Prerequisite: Any electronics/electrical engineering graduate with a good knowledge of RTL design using Verilog HDL.
1: SVA Introduction & Types of Assertions
2: SVA Reference Book
3: SVA Building Blocks, System Functions
4: Writing Sequences and Implication Operators