dots bg

Creating Hard Macros in RISC-V IP

4
(1 rating)
Course Instructor Sweety Dharamdasani
To enroll in this course, please contact the Admin
Contact Admin
dots bg

Course Overview

Course Curriculum

1 Subject

Creating Hard Macros in RISCV IP

3 Learning Materials

Creating Hard Macros in RISC-V IP

Hard Macros Creation : Introduction

Video
9:49

Hard Macros Creation : Script Explanation and Tool Flow

Video
6:57

Intenship project_Creation of Hard Macro

PDF

Course Instructor

tutor image

Sweety Dharamdasani

83 Courses   •   419 Students


Ratings & Reviews

4 /5

1 ratings

●

0 reviews

5

0%

4

100%

3

0%

2

0%

1

0%
GN
Gagana N

●

2 months ago

Get in touch

We'd love to hear from you!

Email us

Our support team is here to help.


elearn@maven-silicon.com

Visit us

Come say hello at our office.

# 21/1A, III Floor, MS Plaza, Gottigere, 
Bannerghatta Road, Bangalore - 560076

Call us

Mon - Sat from 8am to 7pm

080 6909 6300

   Online VLSI Courses

   Online VLSI Courses

   Digital Design - Hands On

   VLSI Design Methodologies

   VLSI System On Chip Design - Overview

Blended VLSI Programs

Blended VLSI Design

Blended VLSI Verification

Blended VLSI Physical Design

Advanced VLSI Verification

Corporate

Advanced VLSI Design

Advanced ASIC Verification

Design for Testability - DFT

SystemVerilog for Verification

University

Campus Connect Program

VLSI SoC Design using Verilog HDL

SoC Design and Verification -- Webinar

VLSI Design using Verilog HDL Webinar

   RISC-V

   RISC-V Instruction Set Architecture

   RISC-V RV32I RTL Design

   RISC-V ISA & RV32I RTL Architecture Design

   RISC-V RV32I RTL Design using Verilog HDL

ARM

ARM Architecture

VLSI Projects

ABLE5 - Aceic’s Bluetooth Low Energy revision 5

AHB2APB Bridge VIP

AXI VIP

SPI VIP