RISC-V Project
Master RISC-V RV32I RTL Design with Maven Silicon, gaining hands-on experience in developing RTL designs for the RV32I instruction set architecture.
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Course Overview
Dive into the world of RISC-V RV32I RTL Design with key modules such as "RISC-V RV32I Reference Guide," "RISC-V RV32I RTL Architecture Design," and "RISC-V RV32I 5 Stage Pipelined RTL Design." Explore the intricacies of RTL design and gain hands-on experience in building a 5-stage pipelined architecture using RISC-V.
Course Curriculum
1 Subject
RISC-V RV32I RTL Design
3 Exercises • 26 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Project: RISC-V RV32I Multi stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V RV32I - Quick Reference Guide for Instrcutions
Course Instructor
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Sivakumar P R
14 Courses • 285 Students
CEO and Founder, Maven Silicon
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