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RISC-V SoC Design

Course Instructor Maven Silicon
To enroll in this course, please contact the Admin
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Course Overview

The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V SoC. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and PLIC. As part of this hands-on course, you will learn SoC architecture, SoC design methodology and flow, SoC interface protocols - AMBA [AXI, AHB, APB], SPI, UART, I2C, GPIO, RISC-V IP design and verification, RISC-V SoC project implementation - RTL, Synthesis, DFT, and PD. This project experience will help you to deal with designing any complex RISC-V processors, RISC-V SoCs and Microcontrollers.

Course Curriculum

16 Subjects

VLSI SoC Design July 2024

1 Exercises • 4 Learning Materials

Introduction to VLSI SoC Design

Electronic System

Video
26:43

Smartphone - SoC - Architecture

Video
9:55

SoC Design

Video
16:59

ASIC Vs FPGA

Video
12:7

Knowledge Check : Introduction to VLSI

Exercise

SoC ASIC Design Flow

5 Learning Materials

ASIC Design Flow

ASIC Design Flow - Part-1 (Specification)

Video
13:4

ASIC Design Flow - Part-2 (Architecture to RTL Design)

Video
9:32

ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)

Video
9:5

ASIC Design Flow - Part-4 (DFT to STA)

Video
10:7

ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)

Video
14:3

RISC-V SoC Design - Methodology, Process & fabrication

6 Learning Materials

RISC-V SoC Design - Methodology, Process and Fabrication

Microcontrollers Vs Complex SoCs

Video
23:6

Computer System Architecture - Von Neuman Vs Harvard

Video
21:52

SoC Design Considerations and RISC-V ISA Overview

Video
22:2

RISC-V Toolchain, CPU, and Memories - Physical Vs Virtual

Video
15:8

MMUs and Interrupt Controllers

Video
17:50

SoC Design - PPA, SoC Manufacturing and Packaging

Video
13:41

Memories and Memory Controllers

4 Learning Materials

Memories and Memory Controllers

Introduction to Memories

Video
5:7

Volatile Memories

Video
27:32

Non-Volatile Memories

Video
12:24

Memory Controllers

Video
11:1

RISC-V Caches

1 Exercises • 5 Learning Materials

Cache Memory

Memory Hierarchy

Video
3:40

Cache Introduction

Video
6:13

Cache Associativity

Video
7:9

Cache Policies

Video
4:19

Cache Coherency

Video
14:58

Knowledge Check : Caches

Exercise

Operating Systems

2 Learning Materials

Operating Systems

Introduction to Operating Systems

Video
14:31

Features of OS

Video
34:50

Virtual Memory Management

1 Exercises • 8 Learning Materials

Virtual Memory Management

VMM Introduction

Video
1:42

Memory Concerns

Video
3:1

Virtual Memory

Video
3:38

Page Table

Video
6:17

Address Translation

Video
14:6

TLB

Video
11:1

Summary

Video
3:39

Knowledge Check : Virtual Memory Management

Exercise

TLB

Video
11:15

RISC-V Processor Architecture

9 Exercises • 41 Learning Materials

RISC-V Overview

RISC-V Overview

Video
9:42

RISC-V Overview Knowledge Check

Exercise

RISC-V Open ISA

RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)

Video
12:17

RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)

Video
9:15

RISC-V - Open ISA

Exercise

RISC-V ISA

RISC-V ISA Part-1 ( introduction)

Video
10:43

RISC-V ISA Part-2 ( RISC-V Registers and Modes)

Video
15:58

RISC-V ISA Part-3 ( introduction to Privileged Architecture)

Video
20:42

RISC-V Base ISA

Base ISA

Video
15:6

RV 32I Instructions

RV32I Base Instructions(R & I type)

Video
23:9

RV32I Base Instructions(S & B Type)

Video
23:30

RV32I Base Instructions(J Type)

Video
15:19

RV32I Base Instructions (U type)

Video
17:11

Knowledge Check : RISC-V ISA

Exercise

RISC-V Extensions

RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)

Video
15:16

RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)

Video
17:12

RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)

Video
14:57

RISC-V F and D Extensions Part-4 (F&D Instructions and examples)

Video
6:10

RISC-V M Extensions

Video
9:13

RISC-V A Extension

Video
16:28

RISC-V C-Extension - Part-1 (Introduction to C Extension)

Video
12:7

RISC-V C-Extension - Part-2 (Instructions available in C Extension)

Video
8:47

Knowledge Check : RISC-V Extensions

Exercise

RISC-V privileged ISA

Privileged Architecture Part-1 (Introduction to Privileged Architecture)

Video
15:4

Privileged Architecture Part-2 (CSR's available in Privileged Architectures)

Video
13:39

RISC-V - Privileged ISA

Exercise

RISC-V Machine ISA

Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)

Video
15:34

Machine ISA Part -2 (mstatus and trap delegation CSR's)

Video
22:36

Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)

Video
16:29

Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)

Video
9:45

RISC-V Machine ISA

Exercise

RISC-V Supervisor ISA

Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)

Video
14:57

Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)

Video
15:48

Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)

Video
21:12

Supervisor ISA Part-4 (Translation Process in SV32 Mode)

Video
19:9

Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)

Video
3:34

Knowledge Check : Supervisor ISA

Exercise

Case Study: RISC-V Operating System

RISC-V OS - Overview

Video
9:29

RISC-V OS - Booting Process

Video
17:3

RISC-V OS - Paging

Video
18:27

RISC-V OS - Kernel Traps

Video
14:24

RISC-V OS - User Traps

Video
18:55

RISC-V Hypervisor ISA

Hypervisor - Part-1 (Introduction to Hypervisor Mode)

Video
11:1

Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)

Video
12:20

Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)

Video
7:45

Hypervisor - Part-4 (VS Mode CSR's)

Video
7:58

Hypervisor - Part-5 (Hypervisor Mode Instructions)

Video
5:34

Knowledge Check : Hypervisor ISA

Exercise

PMA and PMP

RISC-V PMA and PMP

Video
18:4

Knowledge Check : PMA and PMP

Exercise

RISC-V Debug and PLIC

2 Exercises • 6 Learning Materials

Debug

RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)

Video
5:23

RISC-V Debug - Part - 2 (RISC-V Debug System)

Video
7:22

RISC-V Debug - Part - 3 (RISC-V Debug CSR's)

Video
7:00

RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)

Video
18:54

Knowledge Check : RISC-V Debug

Exercise

PLIC

PLIC Part -1 (Introduction to PLIC)

Video
13:25

PLIC Part -2 (Operation of PLIC and various Registers in PLIC)

Video
19:2

Knowledge Check : RISC-V PLIC

Exercise

RISC-V Software Interfaces and Programming

4 Exercises • 13 Learning Materials

Application Binary Interface (ABI)

ABI_V1(Introduction to ABI)

Video
6:54

ABI_V2 (RISC-V Calling Conventions Part-1)

Video
32:44

ABI_V3 (RISC-V Calling Conventions Part-2)

Video
12:9

ABI_V4 (RISC-V Calling Conventions Part-3)

Video
14:45

ABI_V5 (RISC_V ELF Specifications)

Video
41:30

ABI_V6 (RISC-V Linker Relaxation)

Video
6:9

Knowledge Check : Application Binary Interface (ABI)

Exercise

Supervisor Binary Interface (SBI)

SBI_V1 (Introduction to SBI)

Video
20:30

SBI_V2 (Case Study on Open SBI)

Video
1:51

SBI_V3 (SBI Extensions)

Video
32:46

Knowledge Check : Supervisor Binary Interface (SBI)

Exercise

RISC-V Assembly Programming

RISC-V Assembly Programming Part-1 (Assembly Syntax)

Video
27:34

RISC-V Assembly Programming Part-1 (Assembly Examples)

Video
45:38

Knowledge Check : RISC-V Assembly Programming

Exercise

RISC-V Toolchain

RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)

Video
34:12

RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)

Video
33:33

Knowledge Check : RISC-V Toolchain

Exercise

RISC-V Processor IP RTL Design using Verilog HDL

10 Exercises • 33 Learning Materials

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

Knowledge Check : RISC-V RTL Design

Exercise

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

Knowledge Check : RISC-V Pipelined RTL Design

Exercise

Verilog HDL

Introduction to Verilog HDL

Video
23:59

Knowledge Check - Introduction to Verilog HDL

Exercise

Verilog HDL - Quick Reference Guide

PDF

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

Advance Verilog for Verification

Video
29:7

Knowledge Check - Verilog for Verification

Exercise

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Synthesis Coding Style

Video
20:59

Knowledge Check - Synthesis Coding Style

Exercise

Finite State Machine

Video
16:19

Knowledge Check - Finite State Machine

Exercise

Summary

Video
23:58

Verilog HDL : Labs

Instructions - Verilog Labs

PDF

Verilog Lab Manual

PDF

Verilog Labs Folder - Download

ZIP

EDA Tools - Installation Guide

Video
18:50

EDA Tools - User Guide

Video
5:22

Solution to Lab 1

Video
23:43

Solution to Lab 2

Video
10:28

Solution to Lab 3

Video
6:1

Solution to Lab 4

Video
6:53

Solution to Lab 5

Video
6:41

Solution to Lab 6

Video
8:18

Solutions - Verilog Labs - Download

ZIP

RISC-V Processor IP - RTL Verification

30 Exercises • 129 Learning Materials

Code Coverage

Definition of Code Coverage

Video
6:54

Statement and branch coverage

Video
7:17

Condition & Expression Coverage

Video
7:6

Toggle & FSM Coverage

Video
7:47

Questasim commands for Code Coverage

Video
11:26

Makefile for Simulations

Video
8:36

Knowledge Check-Code Coverage 1

Exercise

Code Coverage Labs

Adv. Verilog and Code Coverage Labs User Guide

PDF

Advanced Verilog & Code Coverage Lab Manual - Questasim

PDF

Code Coverage Lab Solutions

Video
25:16

Code Coverage - Reference Book

Code Coverage Reference Book

PDF

Verification Methodology Overview

Introduction to Verification Methodology

Video
22:25

Verification Process

Video
21:46

Reusable TB

Video
7:24

Verification Environment Architecture

Video
19:2

Verification Methodologies & Summary

Video
27:11

Constraint Random Coverage Driven Verification

Video
25:37

Knowledge Check : Verification Methodology Overview

Exercise

SystemVerilog Language Concepts

SV Concepts Agenda

Video
6:38

SV Overview

Video
11:16

SV Randomization & Functional Coverage

Video
6:47

SV TB Architecture

Video
10:19

SV Interface

Video
14:51

SV Virtual Interface

Video
11:40

SV OOP

Video
13:56

SV Transactions

Video
14:46

Knowledge Check : SV language Concepts Overview

Exercise

SystemVerilog Reference Book

SystemVerilog - Quick Reference Guide

PDF

SystemVerilog Datatypes

SystemVerilog Introduction & Logic Data Type

Video
10:50

SV Data Types - 2 State, Struct & Enum

Video
15:27

SV Data Types - Strings,Packages & Summary

Video
9:4

Knowledge Check : Data Types

Exercise

SystemVerilog Memories

SV Memories - Introduction, Packed and Multi Dimensional Arrays

Video
9:45

SV Memories - Dynamic Arrays & Queues

Video
7:41

SV Memories - Associative Arrays, Array Methods & Summary

Video
13:19

Knowledge Check:Memories

Exercise

SystemVerilog Tasks & Functions

SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task

Video
11:32

SV Tasks & Functions - Pass by value & ref and Summary

Video
9:52

Knowledge Check : Tasks & Functions

Exercise

SystemVerilog Interfaces

SV Interfaces - Introduction & Verilog ports Vs SV Interface

Video
18:44

SV Interfaces - Modports & Clocking Block

Video
18:30

SV Interfaces - Examples & Summary

Video
20:49

Knowledge Check:Interface & Clocking Block

Exercise

SystemVerilog Object Oriented Programming - Basics

SV OOP - Introduction, Class Data Type & Objects

Video
15:5

SV OOP - Constructor, Null Object, Object assignments and copy

Video
17:00

SV OOP - Shallow Vs Deep Copy & Summary

Video
17:30

Knowledge Check: Basic OOP

Exercise

SystemVerilog Object Oriented Programming - Advanced

SV OOP - Introduction, Inheritance & Super

Video
20:50

SV OOP - Static properties & methods and Pass by ref

Video
15:23

SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary

Video
21:53

Knowledge Check: Advanced OOP

Exercise

SystemVerilog Randomization

SV Randomization - Introduction, rand and randc

Video
10:58

SV Randomization - Randomize, Pre and Post randomize & Constraints

Video
12:52

SV Randomization - Set Membership, Constraints & Summary

Video
13:22

Knowledge Check: Randomization

Exercise

SystemVerilog Threads, Mailboxes and Semaphores

SV Threads , Events, Mailbox and Semaphores

Video
23:11

Knowledge Check : Threads , Events, Semaphore & Mailbox

Exercise

SystemVerilog Virtual Interface

SV Virtual Interface - Introduction, Implementation & Examples

Video
17:21

Knowledge Check : Virtual Interface

Exercise

SystemVerilog Functional Coverage

SV Functional Coverage - Introduction & CRCDV

Video
15:51

SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary

Video
17:30

Knowledge Check : Functional Coverage

Exercise

Case Study 1 : Dual Port RAM - SystemVerilog TB

Verification Plan

Video
10:18

Testbench Architecture and Verification Flow

Video
8:12

Transaction and Generator

Video
10:55

Interface and Drivers

Video
13:10

Monitors

Video
8:56

Scoreboard and Reference Model

Video
12:59

Environment and Testcases

Video
13:16

Case Study 2 : Maven SoC - SystemVerilog TB

Maven SoC SystemVerilog Verification Environment

Video
10:45

SystemVerilog Labs

SystemVerilog Lab Manual

PDF

Lab 1 Solution : Data Types

Video
17:56

Lab 2 Solution : Interfaces

Video
9:26

Lab 3 Solution : OOP Basics

Video
8:51

Lab 4 Solution : Advanced OOP

Video
18:9

Lab 5 Solution : Randomization

Video
5:41

Lab 6 Solution : Threads, Mailbox & Semaphores

Video
22:2

Lab 7 Solution : Transaction

Video
9:43

Lab 8 Solution : Transactors

Video
9:1