RISC-V SoC Design
Learn the RISC-V SoC Design course with Maven Silicon
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Course Overview
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V SoC. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and PLIC. As part of this hands-on course, you will learn SoC architecture, SoC design methodology and flow, SoC interface protocols - AMBA [AXI, AHB, APB], SPI, UART, I2C, GPIO, RISC-V IP design and verification, RISC-V SoC project implementation - RTL, Synthesis, DFT, and PD. This project experience will help you to deal with designing any complex RISC-V processors, RISC-V SoCs and Microcontrollers.
Schedule of Classes
Course Curriculum
16 Subjects
VLSI SoC Design -V2
1 Exercises • 4 Learning Materials
Introduction to VLSI SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
SoC ASIC Design Flow
5 Learning Materials
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
RISC-V SoC Design - Methodology, Process & fabrication
6 Learning Materials
RISC-V SoC Design - Methodology, Process and Fabrication
Microcontrollers Vs Complex SoCs
Video
00:23:06
Computer System Architecture - Von Neuman Vs Harvard
Video
00:21:52
SoC Design Considerations and RISC-V ISA Overview
Video
00:22:02
RISC-V Toolchain, CPU, and Memories - Physical Vs Virtual
Video
00:15:08
MMUs and Interrupt Controllers
Video
00:17:50
SoC Design - PPA, SoC Manufacturing and Packaging
Video
00:13:41
Memories and Memory Controllers
4 Learning Materials
Memories and Memory Controllers
Introduction to Memories
Video
00:05:07
Volatile Memories
Video
00:27:32
Non-Volatile Memories
Video
00:12:24
Memory Controllers
Video
00:11:01
RISC-V Caches
1 Exercises • 5 Learning Materials
Cache Memory
Memory Hierarchy
Video
00:03:40
Cache Introduction
Video
00:06:13
Cache Associativity
Video
00:07:09
Cache Policies
Video
00:04:19
Cache Coherency
Video
00:14:58
Knowledge Check : Caches
Exercise
Operating Systems
2 Learning Materials
Operating Systems
Introduction to Operating Systems
Video
00:14:31
Features of OS
Video
00:34:50
Virtual Memory Management
1 Exercises • 8 Learning Materials
Virtual Memory Management
VMM Introduction
Video
00:01:42
Memory Concerns
Video
00:03:01
Virtual Memory
Video
00:03:38
Page Table
Video
00:06:17
Address Translation
Video
00:14:06
TLB
Video
00:11:01
Summary
Video
00:03:39
Knowledge Check : Virtual Memory Management
Exercise
TLB
Video
00:11:15
RISC-V Processor Architecture
9 Exercises • 41 Learning Materials
RISC-V Overview
RISC-V Overview
Video
00:09:42
RISC-V Overview Knowledge Check
Exercise
RISC-V Open ISA
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V - Open ISA
Exercise
RISC-V ISA
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
RISC-V Base ISA
Base ISA
Video
00:15:06
RV 32I Instructions
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V Extensions
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
Video
00:15:16
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
Video
00:17:12
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
Video
00:14:57
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
Video
00:06:10
RISC-V M Extensions
Video
00:09:13
RISC-V A Extension
Video
00:16:28
RISC-V C-Extension - Part-1 (Introduction to C Extension)
Video
00:12:07
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Video
00:08:47
Knowledge Check : RISC-V Extensions
Exercise
RISC-V privileged ISA
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Video
00:15:04
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
Video
00:13:39
RISC-V - Privileged ISA
Exercise
RISC-V Machine ISA
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Video
00:15:34
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Video
00:22:36
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Video
00:16:29
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
Video
00:09:45
RISC-V Machine ISA
Exercise
RISC-V Supervisor ISA
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Video
00:14:57
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Video
00:15:48
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Video
00:21:12
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Video
00:19:09
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Video
00:03:34
Knowledge Check : Supervisor ISA
Exercise
Case Study: RISC-V Operating System
RISC-V OS - Overview
Video
00:09:29
RISC-V OS - Booting Process
Video
00:17:03
RISC-V OS - Paging
Video
00:18:27
RISC-V OS - Kernel Traps
Video
00:14:24
RISC-V OS - User Traps
Video
00:18:55
RISC-V Hypervisor ISA
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Video
00:11:01
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Video
00:12:20
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Video
00:07:45
Hypervisor - Part-4 (VS Mode CSR's)
Video
00:07:58
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Video
00:05:34
Knowledge Check : Hypervisor ISA
Exercise
PMA and PMP
RISC-V PMA and PMP
Video
00:18:04
Knowledge Check : PMA and PMP
Exercise
RISC-V Debug and PLIC
2 Exercises • 6 Learning Materials
Debug
RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)
Video
00:05:23
RISC-V Debug - Part - 2 (RISC-V Debug System)
Video
00:07:22
RISC-V Debug - Part - 3 (RISC-V Debug CSR's)
Video
00:07:00
RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)
Video
00:18:54
Knowledge Check : RISC-V Debug
Exercise
PLIC
PLIC Part -1 (Introduction to PLIC)
Video
00:13:25
PLIC Part -2 (Operation of PLIC and various Registers in PLIC)
Video
00:19:02
Knowledge Check : RISC-V PLIC
Exercise
RISC-V Software Interfaces and Programming
4 Exercises • 13 Learning Materials
Application Binary Interface (ABI)
ABI_V1(Introduction to ABI)
Video
00:06:54
ABI_V2 (RISC-V Calling Conventions Part-1)
Video
00:32:44
ABI_V3 (RISC-V Calling Conventions Part-2)
Video
00:12:09
ABI_V4 (RISC-V Calling Conventions Part-3)
Video
00:14:45
ABI_V5 (RISC_V ELF Specifications)
Video
00:41:30
ABI_V6 (RISC-V Linker Relaxation)
Video
00:06:09
Knowledge Check : Application Binary Interface (ABI)
Exercise
Supervisor Binary Interface (SBI)
SBI_V1 (Introduction to SBI)
Video
00:20:30
SBI_V2 (Case Study on Open SBI)
Video
00:01:51
SBI_V3 (SBI Extensions)
Video
00:32:46
Knowledge Check : Supervisor Binary Interface (SBI)
Exercise
RISC-V Assembly Programming
RISC-V Assembly Programming Part-1 (Assembly Syntax)
Video
00:27:34
RISC-V Assembly Programming Part-1 (Assembly Examples)
Video
00:45:38
Knowledge Check : RISC-V Assembly Programming
Exercise
RISC-V Toolchain
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
Video
00:34:12
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Video
00:33:33
Knowledge Check : RISC-V Toolchain
Exercise
RISC-V Processor IP RTL Design using Verilog HDL
2 Exercises • 11 Learning Materials
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
AMBA Protocols - AXI, AHB, APB
25 Learning Materials
Introduction to AMBA
Introduction to AMBA
Video
00:07:10
APB Protocol
APB - Signal Decritption
Video
00:04:28
APB - Data Transfers
Video
00:05:22
AHB Protocol
AHB - Write Read Transfers
Video
00:10:46
AHB - Signal Description
Video
00:07:56
AHB - Locked and Wait Transfers
Video
00:07:18
AHB - Slave Response
Video
00:04:55
AHB - Interconnect
Video
00:09:07
AXI Protocol
Introduction to AXI
Video
00:04:29
AXI - Channel Handshake
Video
00:03:57
AXI - Write and Read Transfers
Video
00:03:56
AXI - Channel Dependencies
Video
00:05:52
AXI - Signal Description
Video
00:08:30
AXI - Atomic Access
Video
00:10:35
AXI - Responses and Strobe Signals
Video
00:06:05
AXI - Transfer Ordering
Video
00:03:02
AXI - Interconnect
Video
00:05:51
Refrence Material
SoC Overview
PDF
RISCV SoC
PDF
SoC Address Map
PDF
SoC Design Requirements
PDF
AXI
PDF
AHB
PDF
APB
PDF
AHB to APB Bridge
PDF
SoC External Interfaces - SPI, UART, I2C, GPIO, JTAG
6 Learning Materials
GPIO
GPIO Protocol Specification
Video
00:17:18
SPI
SPI Protocol Specification
Video
00:14:07
UART
UART Protocol Specification
Video
00:26:47
JTAG
Intdroction to JTAG
Video
00:24:31
JTAG Protocol Specification
Video
00:19:05
I2C
I2C Protocol Specification
Video
00:26:23
Case Study : Microchip Polarfire SoC - RISC-V SoC on FPGA
1 Learning Materials
Case Study : Microchip Polarfire SoC
Case Study : Microchip Polarfile SoC
Video
00:40:27
RISC-V SoC Design project - RTL, DV, DFT & PD
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Verilog HDL Reference Material
Verilog HDL Reference Book
PDF
Verilog HDL - Quick Reference Guide
PDF
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
Course Instructor
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FAQs
1. What is RISC-V SoC Design?
RISC-V SoC Design involves the creation of a System on Chip (SoC) using the RISC-V architecture. This includes designing and integrating a RISC-V processor core along with various peripherals, memory, and I/O interfaces to form a complete chip capable of handling specific applications.
2. What will I learn in a RISC-V SoC Design course?
In this course, you will learn how to design a RISC-V-based SoC, which includes selecting the appropriate RISC-V processor cores, integrating subsystems like memory controllers and peripherals, optimizing the system for performance, power efficiency, and implementing interconnects within the SoC architecture.
3. Do I need prior knowledge of SoC design for this course?
Basic knowledge of digital logic, VLSI design, and RISC-V architecture will be helpful. The course will provide a step-by-step guide to designing RISC-V-based SoCs even for those new to SoC development, covering both high-level architecture and low-level implementation details.
4. What tools will I use for RISC-V SoC Design?
You will use industry-standard tools like Vivado, Cadence, Synopsys Design Compiler, and ModelSim for designing, simulating, and verifying the RISC-V SoC. You’ll also learn how to use RTL design tools for writing hardware description in Verilog or VHDL.
5. What are the key components of a RISC-V SoC?
Key components include the RISC-V processor core (e.g., RV32I, RV64G), memory subsystems (e.g., RAM, ROM), peripheral interfaces (e.g., GPIO, UART, SPI), interconnects (e.g., AXI or AMBA), and custom accelerators that integrate with the processor for enhanced performance.
6. What is the importance of interconnects in RISC-V SoC Design?
Interconnects play a crucial role in RISC-V SoC Design as they provide the data paths between components like the processor core, memory, and peripherals. Efficient interconnect design ensures high data throughput, low latency, and proper communication between various SoC elements.
7. What applications can RISC-V SoC designs be used for?
RISC-V SoC designs can be used in a wide range of applications, including IoT devices, automotive systems, embedded systems, AI accelerators, edge computing, and consumer electronics, where custom, power-efficient, and high-performance processors are required.
8. How does RISC-V SoC Design support customization?
RISC-V provides an open and modular architecture, enabling designers to create custom RISC-V cores and integrate specific instructions or hardware accelerators. This customization makes it suitable for specialized applications that require tailored performance or power consumption characteristics.
9. What is the significance of power and performance optimization in RISC-V SoC Design?
Power and performance optimization is critical in RISC-V SoC Design to ensure that the chip meets the performance requirements of the application while consuming minimal power. Techniques such as clock gating, voltage scaling, and efficient memory management are covered in the course to optimize the SoC design.
10. What career opportunities are available after learning RISC-V SoC Design?
Learning RISC-V SoC Design opens career opportunities in ASIC design, embedded systems development, SoC architecture, and VLSI engineering. You can work as a hardware engineer, SoC designer, or processor architect in companies specializing in custom processors and chip development.
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