RISC-V ISA & RV32I RTL Architecture Design
Explore the intricate architecture of RISC-V ISA and RV32I RTL design with Maven Silicon to uncover the principles behind designing efficient and reliable RTL structures.
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Course Overview
Embark on a comprehensive journey in "RISC-V ISA & RV32I RTL Architecture Design" covering fundamental VLSI concepts, SoC design, and the distinctions between ASIC and FPGA. Navigate through the VLSI design flow, explore digital electronics, and delve into key topics like STA, sequential circuits, memories, and the intricacies of RISC-V ISA. Witness the evolution from RISC-V Instruction Set Architecture to RTL architecture design, culminating in the implementation of a 5-stage pipelined design. Engage with hands-on modules to reinforce your understanding of this dynamic field.
Schedule of Classes
Course Curriculum
1 Subject
RISC-V ISA & RV32I RTL Architecture Design
1 Exercises • 51 Learning Materials
VLSI Introduction
Why VLSI ?
SoC Design
Smart Phone SoC
System On Chip Design Architecture and Methodology
ASIC Vs FPGA
ASIC Vs FPGA
VLSI Design Flow
VLSI Front-End Design Flow Part I
VLSI Front-End Design Flow Part II
VLSI Back-End Design Flow
Knowledge Check : Introduction to VLSI
Digital Electronics
Introduction to Digital Electronics
Number Systems and Codes
Number Systems and Codes
Logic Circuits
Logic Circuits
Combinational Circuits
Combinational Circuits - I
Combinational Circuits - II
Sequential Circuits
Sequential Circuits - I
Sequential Circuits - II
Finite State Machines
FSM
Memories
Memories
STA : Introduction
Why & What is Timing Analysis?
Types of Timing Analysis
False Paths & Multi Cycle Paths
STA in Design Flow
STA: Clock
Clock - Part -1
Clock - Part - 2
STA : Timing Parameters
Timing Parameters in STA - Part-1
Timing Parameters in STA - Part-2
Timing Parameters in STA - Part-3
STA: Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Timing Analysis on Sequential Circuits - Part-2
STA Procedure
STA : Techniques to Improve Timing
Different Techniques to improve timing
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Course Instructor
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Sivakumar P R
17 Courses • 1963 Students
CEO and Founder, Maven Silicon
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