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RISC-V Processor IP Design

Learn the RISC-V Processor IP Design course with Maven Silicon

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(1 rating)
Course Instructors Maven Silicon Deepika Paramesh Nelavalli Kaveri Chandana Maven Silicon Training Support

₹60000.00 ₹120000.00 50% OFF

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Course Overview

The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their own processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined architecture. As part of this hands-on course, you will learn Verilog HDL and create a RISC-V multi-stage Pipeline Processor RTL using Verilog. Also, you will verify the RISC-V RTL IP design using an existing UVM Testbench[Encrypted VIP] and synthesize it. This project experience will help you to deal with designing any complex RISC-V processors.

Course Curriculum

8 Subjects

RISC-V Processor Architecture

9 Exercises41 Learning Materials

RISC-V Overview

RISC-V Overview

Video
00:09:42
FREE

RISC-V Overview Knowledge Check

Exercise

RISC-V Open ISA

RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)

Video
00:12:17

RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)

Video
00:09:15

RISC-V - Open ISA

Exercise

RISC-V ISA

RISC-V ISA Part-1 ( introduction)

Video
00:10:43

RISC-V ISA Part-2 ( RISC-V Registers and Modes)

Video
00:15:58

RISC-V ISA Part-3 ( introduction to Privileged Architecture)

Video
00:20:42

RISC-V Base ISA

Base ISA

Video
00:15:06

RV 32I Instructions

RV32I Base Instructions(R & I type)

Video
00:23:09

RV32I Base Instructions(S & B Type)

Video
00:23:30

RV32I Base Instructions(J Type)

Video
00:15:19

RV32I Base Instructions (U type)

Video
00:17:11

Knowledge Check : RISC-V ISA

Exercise

RISC-V Extensions

RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)

Video
00:15:16

RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)

Video
00:17:12

RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)

Video
00:14:57

RISC-V F and D Extensions Part-4 (F&D Instructions and examples)

Video
00:06:10

RISC-V M Extensions

Video
00:09:13

RISC-V A Extension

Video
00:16:28

RISC-V C-Extension - Part-1 (Introduction to C Extension)

Video
00:12:07

RISC-V C-Extension - Part-2 (Instructions available in C Extension)

Video
00:08:47

Knowledge Check : RISC-V Extensions

Exercise

RISC-V privileged ISA

Privileged Architecture Part-1 (Introduction to Privileged Architecture)

Video
00:15:04

Privileged Architecture Part-2 (CSR's available in Privileged Architectures)

Video
00:13:39

RISC-V - Privileged ISA

Exercise

RISC-V Machine ISA

Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)

Video
00:15:34

Machine ISA Part -2 (mstatus and trap delegation CSR's)

Video
00:22:36

Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)

Video
00:16:29

Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)

Video
00:09:45

RISC-V Machine ISA

Exercise

RISC-V Supervisor ISA

Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)

Video
00:14:57

Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)

Video
00:15:48

Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)

Video
00:21:12

Supervisor ISA Part-4 (Translation Process in SV32 Mode)

Video
00:19:09

Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)

Video
00:03:34

Knowledge Check : Supervisor ISA

Exercise

Case Study: RISC-V Operating System

RISC-V OS - Overview

Video
00:09:29

RISC-V OS - Booting Process

Video
00:17:03

RISC-V OS - Paging

Video
00:18:27

RISC-V OS - Kernel Traps

Video
00:14:24

RISC-V OS - User Traps

Video
00:18:55

RISC-V Hypervisor ISA

Hypervisor - Part-1 (Introduction to Hypervisor Mode)

Video
00:11:01

Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)

Video
00:12:20

Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)

Video
00:07:45

Hypervisor - Part-4 (VS Mode CSR's)

Video
00:07:58

Hypervisor - Part-5 (Hypervisor Mode Instructions)

Video
00:05:34

Knowledge Check : Hypervisor ISA

Exercise

PMA and PMP

RISC-V PMA and PMP

Video
00:18:04

Knowledge Check : PMA and PMP

Exercise

RISC-V Debug

1 Exercises4 Learning Materials

Debug

RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)

Video
00:05:23

RISC-V Debug - Part - 2 (RISC-V Debug System)

Video
00:07:22

RISC-V Debug - Part - 3 (RISC-V Debug CSR's)

Video
00:07:00

RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)

Video
00:18:54

Knowledge Check : RISC-V Debug

Exercise

RISC-V PLIC

1 Exercises2 Learning Materials

PLIC

PLIC Part -1 (Introduction to PLIC)

Video
00:13:25

PLIC Part -2 (Operation of PLIC and various Registers in PLIC)

Video
00:19:02

Knowledge Check : RISC-V PLIC

Exercise

RISC-V Software Interfaces and Programming

4 Exercises13 Learning Materials

Application Binary Interface (ABI)

ABI_V1(Introduction to ABI)

Video
00:06:54

ABI_V2 (RISC-V Calling Conventions Part-1)

Video
00:32:44

ABI_V3 (RISC-V Calling Conventions Part-2)

Video
00:12:09

ABI_V4 (RISC-V Calling Conventions Part-3)

Video
00:14:45

ABI_V5 (RISC_V ELF Specifications)

Video
00:41:30

ABI_V6 (RISC-V Linker Relaxation)

Video
00:06:09

Knowledge Check : Application Binary Interface (ABI)

Exercise

Supervisor Binary Interface (SBI)

SBI_V1 (Introduction to SBI)

Video
00:20:30

SBI_V2 (Case Study on Open SBI)

Video
00:01:51

SBI_V3 (SBI Extensions)

Video
00:32:46

Knowledge Check : Supervisor Binary Interface (SBI)

Exercise

RISC-V Assembly Programming

RISC-V Assembly Programming Part-1 (Assembly Syntax)

Video
00:27:34

RISC-V Assembly Programming Part-1 (Assembly Examples)

Video
00:45:38

Knowledge Check : RISC-V Assembly Programming

Exercise

RISC-V Toolchain

RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)

Video
00:34:12

RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)

Video
00:33:33

Knowledge Check : RISC-V Toolchain

Exercise

RISC-V Caches

1 Exercises5 Learning Materials

Cache Memory

Memory Hierarchy

Video
00:03:40

Cache Introduction

Video
00:06:13

Cache Associativity

Video
00:07:09

Cache Policies

Video
00:04:19

Cache Coherency

Video
00:14:58

Knowledge Check : Caches

Exercise

Virtual Memory Management

1 Exercises8 Learning Materials

Virtual Memory Management

VMM Introduction

Video
00:01:42

Memory Concerns

Video
00:03:01

Virtual Memory

Video
00:03:38

Page Table

Video
00:06:17

Address Translation

Video
00:14:06

TLB

Video
00:11:01

Summary

Video
00:03:39

Knowledge Check : Virtual Memory Management

Exercise

TLB

Video
00:11:15

RISC-V Processor IP RTL Design

10 Exercises33 Learning Materials

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
00:08:36

RISC-V Register File and RV32I Instructions Format

Video
00:12:52

RV32I R Type ALU Datapath

Video
00:09:29

RV32I I Type ALU Datapath

Video
00:06:33

RV32I S Type ALU Datapath - Load & Store

Video
00:13:04

RV32I B Type ALU Datapath

Video
00:08:23

RV32I J Type ALU Datapath JAL & JALR

Video
00:09:26

RV32I U Type ALU Datapath and Summary

Video
00:10:18

Knowledge Check : RISC-V RTL Design

Exercise

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
00:15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
00:16:03

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
00:13:51

Knowledge Check : RISC-V Pipelined RTL Design

Exercise

Verilog HDL

Introduction to Verilog HDL

Video
00:23:59

Knowledge Check - Introduction to Verilog HDL

Exercise

Verilog HDL - Quick Reference Guide

PDF

Data Types

Video
00:30:04

Knowledge Check - Data Types

Exercise

Verilog Operators

Video
00:30:06

Knowledge Check - Verilog Operators

Exercise

Advanced Verilog for Verification

Video
00:29:07

Knowledge Check - Verilog for Verification

Exercise

Assignments

Video
00:23:21

Knowledge Check - Assignments

Exercise

Structured Procedures

Video
00:20:31

Knowledge Check - Structured Procedures

Exercise

Synthesis Coding Style

Video
00:20:59

Knowledge Check - Synthesis Coding Style

Exercise

Finite State Machine

Video
00:16:19

Knowledge Check - Finite State Machine

Exercise

Summary

Video
00:23:58

Verilog HDL : Labs

Instructions - Verilog Labs

PDF

Verilog Lab Manual

PDF

Verilog Labs Folder - Download

ZIP

EDA Tools - Installation Guide

Video
00:18:50

EDA Tools - User Guide

Video
00:05:22

Solution to Lab 1

Video
00:23:43

Solution to Lab 2

Video
00:10:28

Solution to Lab 3

Video
00:06:01

Solution to Lab 4

Video
00:06:53

Solution to Lab 5

Video
00:06:41

Solution to Lab 6

Video
00:08:18

Solutions - Verilog Labs - Download

ZIP

RISC-V Processor - RTL Project

11 Learning Materials

RISC-V Specification

The RISC-V Instruction Set Manual

PDF

MSRV32I Core Design Specification

PDF

RISC-V RV32I Quick Reference Guide

RISC-V RV32I - Quick Reference Guide for Instrcutions

PDF

RISC-V RTL Design

ALU Design

Video
00:11:03

ALU Verification

Video
00:07:48

Integer file design

Video
00:07:12

Integer File Verification

Video
00:09:19

RISC-V RTL Design & Verification Part -1

Video
00:13:41

RISC-V RTL Design & Verification Part -2

Video
00:12:22

RISC-V RTL Design & Verification Part -3

Video
00:19:45

RISC-V RTL Design & Verification Part -4

Video
00:06:21

Course Instructor

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Maven Silicon

312 Courses   •   406579 Students


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Deepika

1 Courses   •   2 Students

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Paramesh Nelavalli

tutor image

Kaveri

tutor image

Chandana

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Maven Silicon Training Support

47 Courses   •   4379 Students

Ratings & Reviews

5 /5

1 ratings

1 reviews

5

100%

4

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3

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2

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1

0%
NH
Nithin H

a year ago

This RISC-V course is well-structured and very beneficial for my career.

FAQs

1. What is RISC-V Processor IP Design?

RISC-V Processor IP Design involves creating custom processor cores based on the RISC-V ISA (Instruction Set Architecture). This course covers designing RISC-V cores, optimizing for performance, power, and area (PPA), and implementing the design as an IP block that can be integrated into larger systems.

2. What will I learn in a RISC-V Processor IP Design course?

In this course, you'll learn the fundamentals of RISC-V architecture, how to design custom processor cores, implement different stages of the processor pipeline, and package the design as an IP for reuse in system-on-chip (SoC) designs, emphasizing low-power and high-performance applications.

3. Do I need prior knowledge of processor design for this course?

A basic understanding of digital logic and processor design principles is recommended. The course will guide you through the RISC-V architecture, from its instruction set to implementing the processor IP. Prior experience with Verilog HDL or similar hardware description languages will also be helpful.

4. What tools will I use in the RISC-V Processor IP Design course?

You will use industry-standard HDL tools like Verilog or VHDL for designing the processor core. Additionally, tools like Vivado, ModelSim, or Cadence will be used for simulation, synthesis, and verification of the RISC-V processor IP.

5. What is the difference between RISC-V Processor IP Design and traditional processor design?

Unlike traditional processor designs, RISC-V processor IP is based on an open-source instruction set, allowing for greater flexibility and customization. This means you can modify the processor design to meet specific application needs, unlike proprietary designs that are locked to a specific vendor.

6. What are the key components of RISC-V Processor IP Design?

Key components include the instruction set (like RV32I), datapath design, control unit design, pipelining, and integration of different processor stages. The design also includes memory management, I/O control, and creating interfaces for integration into SoCs.

7. What are the applications of a custom RISC-V processor?

Custom RISC-V processors can be used in a variety of applications, including embedded systems, IoT devices, high-performance computing, automotive electronics, and AI accelerators, due to the flexibility of the RISC-V architecture and its open-source nature.

8. Can I use RISC-V Processor IP Design for commercial projects?

Yes, one of the major advantages of the RISC-V architecture is that it is open-source and free to use. You can design custom RISC-V processor IP for commercial applications, including product development, SoC design, and embedded systems, without licensing fees.

9. How does RISC-V Processor IP Design support innovation?

Since RISC-V is open and modular, RISC-V Processor IP Design allows developers to innovate by adding custom instructions, integrating accelerators, or optimizing the processor for specific tasks. This can result in highly specialized, efficient, and low-power processor designs tailored to unique application needs.

10. What career opportunities are available after learning RISC-V Processor IP Design?

Learning RISC-V Processor IP Design opens up career opportunities in the semiconductor industry, specifically in ASIC design, SoC development, embedded systems design, and processor architecture. You can work as a VLSI engineer, hardware designer, or IP design specialist for companies working on custom processors or RISC-V-based products.

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