RISC-V Processor IP Design
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Course Overview
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined architecture. As part of this hands-on course, you will learn Verilog HDL and create a RISC-V muti-stage Pipeline Processor RTL using Verilog. Also, you will verify the RISC-V RTL IP design using an existing UVM Testbench[Encrypted VIP] and synthesize it. This project experience will help you to deal with designing any complex RISC-V processors.
Course Curriculum
8 Subjects
RISC-V Processor Architecture
9 Exercises • 42 Learning Materials
RISC-V Overview
RISC-V Overview
RISC-V Overview Knowledge Check
RISC-V Open ISA
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V - Open ISA
RISC-V ISA
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
RISC-V Base ISA
Base ISA
RV 32I Instructions
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V Extensions
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
RISC-V M Extensions
RISC-V A Extension
RISC-V C-Extension - Part-1 (Introduction to C Extension)
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Knowledge Check : RISC-V Extensions
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
RISC-V privileged ISA
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
RISC-V - Privileged ISA
RISC-V Machine ISA
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
RISC-V Machine ISA
RISC-V Supervisor ISA
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Knowledge Check : Supervisor ISA
Case Study: RISC-V Operating System
RISC-V OS - Overview
RISC-V OS - Booting Process
RISC-V OS - Paging
RISC-V OS - Kernel Traps
RISC-V OS - User Traps
RISC-V Hypervisor ISA
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Hypervisor - Part-4 (VS Mode CSR's)
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Knowledge Check : Hypervisor ISA
PMA and PMP
RISC-V PMA and PMP
Knowledge Check : PMA and PMP
RISC-V Debug
1 Exercises • 4 Learning Materials
Debug
RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)
RISC-V Debug - Part - 2 (RISC-V Debug System)
RISC-V Debug - Part - 3 (RISC-V Debug CSR's)
RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)
Knowledge Check : RISC-V Debug
RISC-V PLIC
1 Exercises • 2 Learning Materials
PLIC
PLIC Part -1 (Introduction to PLIC)
PLIC Part -2 (Operation of PLIC and various Registers in PLIC)
Knowledge Check : RISC-V PLIC
RISC-V Software Interfaces and Programming
4 Exercises • 13 Learning Materials
Application Binary Interface (ABI)
ABI_V1(Introduction to ABI)
ABI_V2 (RISC-V Calling Conventions Part-1)
ABI_V3 (RISC-V Calling Conventions Part-2)
ABI_V4 (RISC-V Calling Conventions Part-3)
ABI_V5 (RISC_V ELF Specifications)
ABI_V6 (RISC-V Linker Relaxation)
Knowledge Check : Application Binary Interface (ABI)
Supervisor Binary Interface (SBI)
SBI_V1 (Introduction to SBI)
SBI_V2 (Case Study on Open SBI)
SBI_V3 (SBI Extensions)
Knowledge Check : Supervisor Binary Interface (SBI)
RISC-V Assembly Programming
RISC-V Assembly Programming Part-1 (Assembly Syntax)
RISC-V Assembly Programming Part-1 (Assembly Examples)
Knowledge Check : RISC-V Assembly Programming
RISC-V Toolchain
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Knowledge Check : RISC-V Toolchain
RISC-V Caches
1 Exercises • 5 Learning Materials
Cache Memory
Memory Hierarchy
Cache Introduction
Cache Associativity
Cache Policies
Cache Coherency
Knowledge Check : Caches
Virtual Memory Management
1 Exercises • 8 Learning Materials
Virtual Memory Management
VMM Introduction
Memory Concerns
Virtual Memory
Page Table
Address Translation
TLB
Summary
Knowledge Check : Virtual Memory Management
TLB
RISC-V Processor IP RTL Design
10 Exercises • 33 Learning Materials
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Verilog HDL
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Verilog HDL - Quick Reference Guide
Data Types
Knowledge Check - Data Types
Verilog Operators
Knowledge Check - Verilog Operators
Advance Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Knowledge Check - Assignments
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Knowledge Check - Finite State Machine
Summary
Verilog HDL : Labs
Instructions - Verilog Labs
Verilog Lab Manual
Verilog Labs Folder - Download
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab 1
Solution to Lab 2
Solution to Lab 3
Solution to Lab 4
Solution to Lab 5
Solution to Lab 6
Solutions - Verilog Labs - Download
RISC-V Processor - RTL Project
11 Learning Materials
RISC-V Specification
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V RV32I Quick Reference Guide
RISC-V RV32I - Quick Reference Guide for Instrcutions
RISC-V RTL Design
ALU Design
ALU Verification
Integer file design
Integer File Verification
RISC-V RTL Design & Verification Part -1
RISC-V RTL Design & Verification Part -2
RISC-V RTL Design & Verification Part -3
RISC-V RTL Design & Verification Part -4
Course Instructor
Sweety Dharamdasani
83 Courses • 334 Students
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