The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to verify a RISC-V processor efficiently. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined architecture. As part of this hands-on course, you will learn Verification methodologies, SystemVerilog, Universal Verification Methodology [UVM], SVA, Code and functional coverage, and verify a multi-stage Pipeline Processor RTL using UVM. This project experience will help you to deal with verifying any complex RISC-V processors.