RISC-V Processor IP Verification
Learn the RISC-V Processor IP Verification course with Maven Silicon
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Course Overview
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux, as it's based on the RISC-V open ISA [Instruction Set Architecture], which is open and license-free. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their processors and chips with their innovations. So, it's the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to verify a RISC-V processor efficiently. This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture - Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined architecture. As part of this hands-on course, you will learn Verification methodologies, SystemVerilog, Universal Verification Methodology [UVM], SVA, Code and functional coverage, and verify a multi-stage Pipeline Processor RTL using UVM. This project experience will help you to deal with verifying any complex RISC-V processors.
Course Curriculum
8 Subjects
RISC-V Processor Architecture
9 Exercises • 41 Learning Materials
RISC-V Overview
RISC-V Overview
RISC-V Overview Knowledge Check
RISC-V Open ISA
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V - Open ISA
RISC-V ISA
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
RISC-V Base ISA
Base ISA
RV 32I Instructions
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V Extensions
RISC-V F and D Extensions Part-1 (How to represent Floating Point Numbers)
RISC-V F and D Extensions Part-2 (Overview on IEEE 754 - 2008 standard)
RISC-V F and D Extensions Part-3 (Floating Point Registers and Instruction Encoding)
RISC-V F and D Extensions Part-4 (F&D Instructions and examples)
RISC-V M Extensions
RISC-V A Extension
RISC-V C-Extension - Part-1 (Introduction to C Extension)
RISC-V C-Extension - Part-2 (Instructions available in C Extension)
Knowledge Check : RISC-V Extensions
RISC-V privileged ISA
Privileged Architecture Part-1 (Introduction to Privileged Architecture)
Privileged Architecture Part-2 (CSR's available in Privileged Architectures)
RISC-V - Privileged ISA
RISC-V Machine ISA
Machine ISA Part -1 ( Introduction to Machine ISA and few CSR's)
Machine ISA Part -2 (mstatus and trap delegation CSR's)
Machine ISA Part -3 (Trap Handling Process and the corresponding CSR's)
Machine ISA Part -4 (Machine Timer Registers and Machine Mode Privileged Instructions)
RISC-V Machine ISA
RISC-V Supervisor ISA
Supervisor ISA Part-1 (Introduction to Supervisor ISA and ststaus CSR)
Supervisor ISA Part-2 (CSR's available for Supervisor Mode & Introduction to Translation Process)
Supervisor ISA Part-3 ( satp CSR, various translation modes and page sizes)
Supervisor ISA Part-4 (Translation Process in SV32 Mode)
Supervisor ISA Part-5 (SV 39, SV 48 and SV 57 Translation Modes)
Knowledge Check : Supervisor ISA
Case Study: RISC-V Operating System
RISC-V OS - Overview
RISC-V OS - Booting Process
RISC-V OS - Paging
RISC-V OS - Kernel Traps
RISC-V OS - User Traps
RISC-V Hypervisor ISA
Hypervisor - Part-1 (Introduction to Hypervisor Mode)
Hypervisor - Part-2 ( Hypervisor Mode CSR's Part-1)
Hypervisor - Part-3 (Hypervisor Mode CSR's Part-2)
Hypervisor - Part-4 (VS Mode CSR's)
Hypervisor - Part-5 (Hypervisor Mode Instructions)
Knowledge Check : Hypervisor ISA
PMA and PMP
RISC-V PMA and PMP
Knowledge Check : PMA and PMP
RISC-V PLIC
1 Exercises • 2 Learning Materials
PLIC
PLIC Part -1 (Introduction to PLIC)
PLIC Part -2 (Operation of PLIC and various Registers in PLIC)
Knowledge Check : RISC-V PLIC
RISC-V Debug
1 Exercises • 4 Learning Materials
Debug
RISC-V Debug - Part - 1 (Introduction to RISC-V Debug)
RISC-V Debug - Part - 2 (RISC-V Debug System)
RISC-V Debug - Part - 3 (RISC-V Debug CSR's)
RISC-V Debug - Part - 4 (Debug CSR's and Debug Process)
Knowledge Check : RISC-V Debug
RISC-V Software Interfaces and Programming
4 Exercises • 13 Learning Materials
Application Binary Interface (ABI)
ABI_V1(Introduction to ABI)
ABI_V2 (RISC-V Calling Conventions Part-1)
ABI_V3 (RISC-V Calling Conventions Part-2)
ABI_V4 (RISC-V Calling Conventions Part-3)
ABI_V5 (RISC_V ELF Specifications)
ABI_V6 (RISC-V Linker Relaxation)
Knowledge Check : Application Binary Interface (ABI)
Supervisor Binary Interface (SBI)
SBI_V1 (Introduction to SBI)
SBI_V2 (Case Study on Open SBI)
SBI_V3 (SBI Extensions)
Knowledge Check : Supervisor Binary Interface (SBI)
RISC-V Assembly Programming
RISC-V Assembly Programming Part-1 (Assembly Syntax)
RISC-V Assembly Programming Part-1 (Assembly Examples)
Knowledge Check : RISC-V Assembly Programming
RISC-V Toolchain
RISC-V Toolchain Part-1 (Introduction to RISC-V GCC Toolchain)
RISC-V Toolchain Part-2 (RISC-V Linker Scripts and ISS)
Knowledge Check : RISC-V Toolchain
RISC-V Caches
1 Exercises • 5 Learning Materials
Cache Memory
Memory Hierarchy
Cache Introduction
Cache Associativity
Cache Policies
Cache Coherency
Knowledge Check : Caches
Virtual Memory Management
1 Exercises • 8 Learning Materials
Virtual Memory Management
VMM Introduction
Memory Concerns
Virtual Memory
Page Table
Address Translation
TLB
Summary
Knowledge Check : Virtual Memory Management
TLB
RISC-V Processor IP - RTL Verification
30 Exercises • 129 Learning Materials
Code Coverage
Definition of Code Coverage
Statement and branch coverage
Condition & Expression Coverage
Toggle & FSM Coverage
Questasim commands for Code Coverage
Makefile for Simulations
Knowledge Check-Code Coverage 1
Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
Advanced Verilog & Code Coverage Lab Manual - Questasim
Code Coverage Lab Solutions
Code Coverage - Reference Book
Code Coverage Reference Book
Verification Methodology Overview
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Verification Methodologies & Summary
Constraint Random Coverage Driven Verification
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Randomization & Functional Coverage
SV TB Architecture
SV Interface
SV Virtual Interface
SV OOP
SV Transactions
Knowledge Check : SV language Concepts Overview
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
SV Data Types - 2 State, Struct & Enum
SV Data Types - Strings,Packages & Summary
Knowledge Check : Data Types
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
SV Memories - Dynamic Arrays & Queues
SV Memories - Associative Arrays, Array Methods & Summary
Knowledge Check:Memories
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
SV Tasks & Functions - Pass by value & ref and Summary
Knowledge Check : Tasks & Functions
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
SV Interfaces - Modports & Clocking Block
SV Interfaces - Examples & Summary
Knowledge Check:Interface & Clocking Block
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
SV OOP - Constructor, Null Object, Object assignments and copy
SV OOP - Shallow Vs Deep Copy & Summary
Knowledge Check: Basic OOP
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
SV OOP - Static properties & methods and Pass by ref
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Knowledge Check: Advanced OOP
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
SV Randomization - Randomize, Pre and Post randomize & Constraints
SV Randomization - Set Membership, Constraints & Summary
Knowledge Check: Randomization
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Knowledge Check : Threads , Events, Semaphore & Mailbox
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Knowledge Check : Virtual Interface
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Knowledge Check : Functional Coverage
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Testbench Architecture and Verification Flow
Transaction and Generator
Interface and Drivers
Monitors
Scoreboard and Reference Model
Environment and Testcases
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
SystemVerilog Labs
SystemVerilog Lab Manual
Lab 1 Solution : Data Types
Lab 2 Solution : Interfaces
Lab 3 Solution : OOP Basics
Lab 4 Solution : Advanced OOP
Lab 5 Solution : Randomization
Lab 6 Solution : Threads, Mailbox & Semaphores
Lab 7 Solution : Transaction
Lab 8 Solution : Transactors
Lab 9 Solution : Scoreboard & Reference Model
Lab 10 Solution : Environment & Testcases
SVA Introduction & Types of Assertions
What are Assertions?
Necessity of using SystemVerilog Assertions
Types of Assertions
SVA - Knowledge Check - 1
SVA Building Blocks, System Functions
SVA Building Blocks
System Functions
SVA - Knowledge Check - 2
Writing Sequences and Implication Operators
How to write sequences?
Implication Operators
Exercise based on Implication Operators and Timing Windows
SVA - Knowledge Check - 3
Repetition Operators and Sequence Composition
Repetition Operators
Sequence Composition
Methods for Sequences
SVA - Knowledge Check - 4
Miscellaneous Concepts and Connecting Assertions to DUT
Miscellaneous Concepts in SVA
Connecting Assertions to DUT
SVA - Knowledge Check - 5
SVA Labs
SVA Labs User Guide
SVA Lab Solution
SVA Lab Manual
SVA Reference Book
SVA Reference Book
Universal Verification Methodology Overview
Introduction to UVM
UVM Concepts
UVM SoC TB
UVM AHB UVC
UVM SoC TB Examples
Knowledge Check : Introduction to UVM
UVM Reference Book
UVM - Quick Reference Guide
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
UVM Base Class Hierarchy
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
UVM Factory
UVM Factory - Importance of using factory
UVM Factory - Registration Process
UVM Factory - Create Method and Factory Overriding
Knowledge Check - UVM Factory
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
UVM Stimulus Modelling - Overriding the predefined do_ methods
UVM - TB Overview
Knowledge Check - UVM Stimulus Modelling & TB Overview
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
UVM Reporting Mechanism
Knowledge Check - UVM Phases & Reporting Mechanism
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
UVM TLM Ports - TLM FIFO and Analysis Ports
UVM Configuration - Introduction to Configuration Facility
UVM Configuration - Configuration class and Configuration of Virtual Interface
Knowledge Check - UVM TLM Ports and Configuration
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Knowledge Check - UVM - Creating UVM Testbench Components
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
UVM Sequences - Starting the sequences and Default Sequence
Knowledge Check - UVM Sequences
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
UVM Virtual Sequences & Virtual Sequencers - implementation
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
UVM Callbacks & Events
UVM Callbacks
UVM Events
Knowledge Check - UVM Callbacks & Events
UVM - Creating Scoreboard
UVM Creating Scoreboard
Knowledge Check - UVM - Creating Scoreboard
UVM Labs
UVM Lab Manual
Lab1 Solution : Stimulus Modeling
Lab2 Solution : Factory Overriding
Lab3 Solution : UVM Phases
Lab4 Solution : Creating UVM agent
Lab5 Solution : UVM Sequences
Lab6 Solution : Virtual Interface
Lab7 Solution : Agent Integration
Lab8 Solution : UVM Scoreboard
Lab9 Solution : SoC - UVM VE implementation
Lab10 Solution : Coverage & Regression
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
UVM RAL - Adapter, Predictor and Integration
UVM RAL - Definition of Register Sequences
Knowledge Check - UVM RAL
RISC-V Processor Verification - Project
7 Learning Materials
RISC-V RV32I Quick reference Guides
RISC-V RV32I reference Card for V-Plan
RISC-V RV32I - Quick Reference Guide for Instrcutions
RISC-V Specification
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V Processor Verification
RISC-V Verification Plan-1
RISC-V Verification Plan -2
RISC-V TB Architecture
Course Instructor
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Maven Silicon
306 Courses • 393407 Students
Deepika
1 Courses • 2 Students
Paramesh Nelavalli
Kaveri
Chandana
Maven Silicon Training Support
47 Courses • 4326 Students
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