RISC-V RV32I RTL Design using Verilog HDL
Embark on the journey of RISC-V RV32I RTL Design using Verilog HDL with Maven Silicon, developing practical skills in implementing RTL structures for RISC-V.
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Course Overview
Explore the intricacies of "RISC-V RV32I RTL Design using Verilog HDL" with a holistic approach. Begin with a solid foundation in RISC-V Instruction Set Architecture and progress through RTL architecture design, including a 5-stage pipelined implementation. Immerse yourself in Verilog HDL, mastering data types, operators, and advanced techniques for verification. Engage in hands-on labs to reinforce your skills and culminate in the creation of a multi-stage pipeline processor design. Cap off your journey with a final test, showcasing your prowess in RISC-V design using Verilog HDL.
Course Curriculum
1 Subject
RISC-V RV32I RTL Design using Verilog HDL
12 Exercises • 57 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
Knowledge Check : RISC-V ISA
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Design
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V Pipelined RTL Design
Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Verilog HDL Reference Guide
Verilog HDL - Quick Reference Guide
Verilog HDL: Data Types
Data Types
Knowledge Check - Data Types
Verilog HDL: Operators
Verilog Operators
Knowledge Check - Verilog Operators
Advanced Verilog for Verification
Advance Verilog for Verification
Knowledge Check - Verilog for Verification
Verilog HDL: Assignments
Assignments
Knowledge Check - Assignments
Verilog HDL: Structured Procedures
Structured Procedures
Knowledge Check - Structured Procedures
Verilog HDL : Synthesis Coding Style
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Verilog HDL: Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Summary - Verilog HDL
Summary
Verilog HDL : Labs
Instructions - Verilog Labs
Verilog Lab Manual
EDA Tools - Installation Guide
EDA Tools - User Guide
Solution to Lab 1
Solution to Lab 2
Solution to Lab 3
Solution to Lab 4
Solution to Lab 5
Solution to Lab 6
Project: RISC-V RV32I Multi stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
MSRV32I Core Design Specification
RISC-V RV32I - Quick Reference Guide for Instrcutions
Final Test: RISCV design
RISCV design
RISC-V RTL Design
ALU Design
ALU Verification
Integer file design
Integer File Verification
RISC-V RTL Design & Verification Part -1
RISC-V RTL Design & Verification Part -2
RISC-V RTL Design & Verification Part -3
RISC-V RTL Design & Verification Part -4
Course Instructor
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Sivakumar P R
17 Courses • 1963 Students
CEO and Founder, Maven Silicon
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