RISC-V RV32I RTL Verification using UVM
Validate RISC-V RV32I RTL designs effectively with Maven Silicon's UVM-based verification course, mastering industry-standard techniques for reliable designs.
/CourseBundles(32)/672-RISC-V_RV32I_RTL_Verification_using_UVM-min.png)
Course Overview
Explore "RISC-V RV32I RTL Verification using UVM," a course delving into RISC-V architecture. Begin with the Instruction Set Architecture, RV32I processor, and a 5-stage pipeline processor. Grasp Linux OS fundamentals. Transition to UVM, covering its architecture, stimulus modeling, and testbench phases. Engage in hands-on labs for UVM setup, sequence creation, and register abstraction. Enhance your RTL verification skills with UVM, ensuring a comprehensive understanding.
Course Curriculum
1 Subject
RISC-V RV32I RTL Verification using UVM
14 Exercises • 71 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
RISC-V ISA Part-1 ( introduction)
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Base ISA
RV32I Base Instructions(R & I type)
RV32I Base Instructions(S & B Type)
RV32I Base Instructions(J Type)
RV32I Base Instructions (U type)
RISC-V RV32I Processor
RISC-V Execution Stages and Flow
RISC-V Register File and RV32I Instructions Format
RV32I R Type ALU Datapath
RV32I I Type ALU Datapath
RV32I S Type ALU Datapath - Load & Store
RV32I B Type ALU Datapath
RV32I J Type ALU Datapath JAL & JALR
RV32I U Type ALU Datapath and Summary
Knowledge Check : RISC-V RTL Architecture Design
RISC-V RV32I 5 Stage Pipeline Processor
CPU Performance and RISC-V 5 Stage Pipeline Overview
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Knowledge Check : RISC-V RV32I 5 Stage Pipelined RTL Design
Linux Operating System
Introduction to Linux Operating System
vi Text Editor
Universal Verification Methodology Overview
UVM_Introduction
Advanced_UVM_CaseStudies
Knowledge Check : Introduction to UVM
UVM Reference Guide
UVM - Quick Reference Guide
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
UVM Base Class Hierarchy
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
UVM Factory
UVM Factory - Importance of using factory
UVM Factory - Registration Process
UVM Factory - Create Method and Factory Overriding
Knowledge Check - UVM Factory
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
UVM Stimulus Modelling - Overriding the predefined do_ methods
UVM - TB Overview
Knowledge Check - UVM Stimulus Modelling & TB Overview
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
UVM Reporting Mechanism
Knowledge Check - UVM Phases & Reporting Mechanism
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
UVM TLM Ports - TLM FIFO and Analysis Ports
UVM Configuration - Introduction to Configuration Facility
UVM Configuration - Configuration class and Configuration of Virtual Interface
Knowledge Check - UVM TLM Ports and Configuration
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Knowledge Check - UVM - Creating UVM Testbench Components
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
UVM Sequences - Starting the sequences and Default Sequence
Knowledge Check - UVM Sequences
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
UVM Virtual Sequences & Virtual Sequencers - implementation
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
UVM Callbacks & Events
UVM Callbacks
UVM Events
Knowledge Check - UVM Callbacks & Events
UVM - Creating Scoreboard
UVM Creating Scoreboard
Knowledge Check - UVM - Creating Scoreboard
UVM - Register Abstraction Layer
UVM RAL - Adapter, Predictor and Integration
UVM RAL - Definition of Register Sequences
UVM RAL - Intro & Definition of Register Block
Knowledge Check - UVM RAL
UVM - CaseStudies
Advanced_UVM_CaseStudies
UVM Lab Setup guide - reference manuals
UVM Labs User Guide
VPN Configuration Guide
UVM Labs
UVM Lab Manual
Lab1 Solution : Stimulus Modeling
Lab2 Solution : Factory Overriding
Lab3 Solution : UVM Phases
Lab4 Solution : Creating UVM agent
Lab5 Solution : UVM Sequences
Lab6 Solution : Virtual Interface
Lab7 Solution : Agent Integration
Lab8 Solution : UVM Socreboard
Lab9 Solution : SoC - UVM VE implementation
Lab10 Solution : Coverage & Regression
RISC-V Processor Verification
RISC-V Verification Plan-1
RISC-V Verification Plan -2
RISC-V TB Architecture
Course Instructor
/101894-Maven_Logo_(elearn_profile_pic)_(2).png){kind=logo}
Sivakumar P R
14 Courses • 270 Students
CEO and Founder, Maven Silicon
Ratings & Reviews
4.7 /5
9 ratings
●
8 reviews
5
4
3
2
1
Get in touch
We'd love to hear from you!
Visit us
Come say hello at our office.
# 21/1A, III Floor, MS Plaza, Gottigere,
Bannerghatta Road, Bangalore - 560076
Call us
Mon - Sat from 8am to 7pm
080 6909 6300
Online VLSI Courses
Digital Design - Hands On
VLSI Design Methodologies
VLSI System On Chip Design - Overview
Blended VLSI Programs
Blended VLSI Physical Design
Corporate
By clicking on Continue, I accept the Terms & Conditions,
Privacy Policy & Refund Policy