RISC-V RV32I RTL Verification using UVM
Validate RISC-V RV32I RTL designs effectively with Maven Silicon's UVM-based verification course, mastering industry-standard techniques for reliable designs.
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Course Instructor
Maven Silicon
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Course Overview
Explore "RISC-V RV32I RTL Verification using UVM," a course delving into RISC-V architecture. Begin with the Instruction Set Architecture, RV32I processor, and a 5-stage pipeline processor. Grasp Linux OS fundamentals. Transition to UVM, covering its architecture, stimulus modeling, and testbench phases. Engage in hands-on labs for UVM setup, sequence creation, and register abstraction. Enhance your RTL verification skills with UVM, ensuring a comprehensive understanding.
Course Curriculum
1 Subject
RISC-V RV32I RTL Verification using UVM
14 Exercises • 71 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
9:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
9:15
RISC-V ISA Part-1 ( introduction)
Video
10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
20:42
Base ISA
Video
15:6
RV32I Base Instructions(R & I type)
Video
23:9
RV32I Base Instructions(S & B Type)
Video
23:30
RV32I Base Instructions(J Type)
Video
15:19
RV32I Base Instructions (U type)
Video
17:11
RISC-V RV32I Processor
RISC-V Execution Stages and Flow
Video
8:36
RISC-V Register File and RV32I Instructions Format
Video
12:52
RV32I R Type ALU Datapath
Video
9:29
RV32I I Type ALU Datapath
Video
6:33
RV32I S Type ALU Datapath - Load & Store
Video
13:4
RV32I B Type ALU Datapath
Video
8:23
RV32I J Type ALU Datapath JAL & JALR
Video
9:26
RV32I U Type ALU Datapath and Summary
Video
10:18
Knowledge Check : RISC-V RTL Architecture Design
Exercise
RISC-V RV32I 5 Stage Pipeline Processor
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
16:3
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
13:51
Knowledge Check : RISC-V RV32I 5 Stage Pipelined RTL Design
Exercise
Linux Operating System
Introduction to Linux Operating System
Video
1:15:00
vi Text Editor
Video
31:00
Universal Verification Methodology Overview
UVM_Introduction
Video
43:18
Advanced_UVM_CaseStudies
Video
48:13
Knowledge Check : Introduction to UVM
Exercise
UVM Reference Guide
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
13:48
UVM Base Class Hierarchy
Video
14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
11:19
UVM Factory - Registration Process
Video
6:2
UVM Factory - Create Method and Factory Overriding
Video
11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
10:41
UVM - TB Overview
Video
10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
13:13
UVM Reporting Mechanism
Video
15:1
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
13:1
UVM Configuration - Introduction to Configuration Facility
Video
13:2
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
9:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
15:1
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
8:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
9:23
UVM Events
Video
9:6
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
9:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM - Register Abstraction Layer
UVM RAL - Adapter, Predictor and Integration
Video
20:36
UVM RAL - Definition of Register Sequences
Video
11:55
UVM RAL - Intro & Definition of Register Block
Video
15:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
48:13
UVM Lab Setup guide - reference manuals
UVM Labs User Guide
PDF
VPN Configuration Guide
PDF
UVM Labs
UVM Lab Manual
PDF
Lab1 Solution : Stimulus Modeling
Video
16:2
Lab2 Solution : Factory Overriding
Video
8:19
Lab3 Solution : UVM Phases
Video
10:22
Lab4 Solution : Creating UVM agent
Video
11:44
Lab5 Solution : UVM Sequences
Video
13:22
Lab6 Solution : Virtual Interface
Video
5:50
Lab7 Solution : Agent Integration
Video
8:12
Lab8 Solution : UVM Socreboard
Video
6:39
Lab9 Solution : SoC - UVM VE implementation
Video
8:41
Lab10 Solution : Coverage & Regression
Video
4:33
RISC-V Processor Verification
RISC-V Verification Plan-1
Video
2:10
RISC-V Verification Plan -2
Video
2:21
RISC-V TB Architecture
Video
11:2
Course Instructor
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Maven Silicon
262 Courses • 326074 Students
Ratings & Reviews
4.7 /5
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FAQs
1. What will I learn in a RISC-V RV32I RTL Verification using UVM course?
In this course, you'll learn how to verify the RISC-V RV32I RTL design using UVM (Universal Verification Methodology). You'll explore testbenches, coverage models, and various UVM constructs to ensure functional correctness and efficiency in the processor design.
2. Do I need prior knowledge of UVM for this course?
While prior knowledge of UVM is not mandatory, a basic understanding of digital design and SystemVerilog is helpful. The course will cover the essentials of UVM, including testbenches and verification components for RISC-V RV32I designs.
3. What tools are used in the RISC-V RV32I RTL Verification using UVM course?
The course uses SystemVerilog and UVM for creating verification environments, alongside simulation tools like ModelSim, VCS, or Cadence Xcelium for running simulations and performing coverage analysis of the RISC-V RV32I RTL design.
4. Who is this course suitable for?
This course is ideal for digital design engineers, VLSI professionals, and students who want to specialize in verification. If you are familiar with RISC-V, SystemVerilog, and UVM, this course will enhance your verification skills in RTL design.
5. What is the role of UVM in RTL verification?
UVM plays a crucial role in RTL verification by providing a standard methodology to create reusable, scalable, and modular testbenches for verifying designs like RISC-V RV32I. UVM facilitates stimulus generation, coverage analysis, and fault injection, ensuring thorough verification of the design.
6. What does the verification process for RV32I RTL include?
The verification process includes developing a comprehensive testbench using UVM, writing functional verification tests, performing directed and random testing, and checking for code coverage and functional coverage to ensure the correctness of the RISC-V RV32I processor design.
7. What are some key topics covered in the RISC-V RV32I RTL verification course?
Key topics include creating a UVM testbench for RISC-V RV32I RTL, writing functional and directed tests, performing random testing with UVM sequences, and analyzing test results to identify design issues in the RISC-V processor implementation.
8. Can I apply what I learn in this course to other processor architectures?
Yes, the skills learned in this course are applicable to verifying other processor architectures. Once you understand UVM-based verification for RISC-V RV32I, you can adapt the techniques for verifying designs based on other RISC-V extensions or different ISAs.
9. How is UVM used to ensure functional correctness in RISC-V RV32I RTL?
UVM enables the creation of modular and reusable verification components like stimulus generators, checkers, and coverage monitors. These components work together to ensure that all possible instruction sequences, corner cases, and design scenarios are tested, ensuring the functional correctness of the RISC-V RV32I RTL design.
10. What career benefits does learning RISC-V RV32I RTL verification using UVM provide?
Learning RISC-V RV32I RTL verification using UVM provides you with essential skills in verifying complex processor designs and VLSI systems. This expertise is in high demand in semiconductor companies, especially those involved in developing custom processors and ASICs based on the RISC-V architecture.
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