SystemVerilog for Verification
Boost your team's verification skills with custom training in SystemVerilog from Maven Silicon, developing expertise for robust and efficient verification processes.
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Course Overview
Welcome to the SystemVerilog for Verification course! This comprehensive program covers Verification Methodology, SystemVerilog Language Concepts, and introduces advanced topics like Object-Oriented Programming and Randomization. Engage in hands-on Labs, explore Assertion-Based Verification with SVA, and tackle real-world case studies. Reinforce your knowledge with a dedicated Module Test to ensure a solid understanding of SystemVerilog for Verification.
Course Curriculum
1 Subject
SystemVerilog for Verification
18 Exercises • 80 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Constraint Random Coverage Driven Verification
Verification Methodologies & Summary
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Transactions
SV Interface
SV Virtual Interface
SV OOP
SV Randomization & Functional Coverage
SV TB Architecture
Knowledge Check : SV language Concepts Overview
SystemVerilog Reference Book
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
SV Data Types - 2 State, Struct & Enum
SV Data Types - Strings,Packages & Summary
Knowledge Check : Data Types
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
SV Memories - Dynamic Arrays & Queues
SV Memories - Associative Arrays, Array Methods & Summary
Knowledge Check:Memories
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
SV Tasks & Functions - Pass by value & ref and Summary
Knowledge Check : Tasks & Functions
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
SV Interfaces - Modports & Clocking Block
SV Interfaces - Examples & Summary
Knowledge Check:Interface & Clocking Block
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
SV OOP - Constructor, Null Object, Object assignments and copy
SV OOP - Shallow Vs Deep Copy & Summary
Knowledge Check: Basic OOP
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
SV OOP - Static properties & methods and Pass by ref
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Knowledge Check: Advanced OOP
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
SV Randomization - Randomize, Pre and Post randomize & Constraints
SV Randomization - Set Membership, Constraints & Summary
Knowledge Check: Randomization
SystemVerilog Threads
SV Threads, Events, Mailbox and Semaphores
Knowledge Check : Threads , Events, Semaphore & Mailbox
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Knowledge Check : Virtual Interface
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Knowledge Check : Functional Coverage
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Testbench Architecture and Verification Flow
Transaction and Generator
Interface and Drivers
Monitors
Scoreboard and Reference Model
Environment and Testcases
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
SystemVerilog Labs
SV lab Manual - Questasim
SystemVerilog Lab Manual - for Synopsys VCS
Makefile Usage
Lab 1 Solution : Data Types
Lab 2 Solution : Interfaces
Lab 3 Solution : OOP Basics
Lab 4 Solution : Advanced OOP
Lab 5 Solution : Randomization
Lab 6 Solution : Threads, Mailbox & Semaphores
Lab 7 Solution : Transaction
Lab 8 Solution : Transactors
Lab 9 Solution : Scoreboard & Reference Model
Lab 10 Solution : Environment & Testcases
SVA : Introduction & Types of Assertions
What are Assertions?
Necessity of using SystemVerilog Assertions
Types of Assertions
SVA - Knowledge Check - 1
SystemVerilog Assertions SVA : Reference Book
SVA Reference Book
SVA : Building Blocks, System Functions
SVA Building Blocks
System Functions
SVA - Knowledge Check - 2
SVA : Writing Sequences and Implication Operators
How to write sequences?
Implication Operators
Exercise based on Implication Operators and Timing Windows
SVA - Knowledge Check - 3
SVA : Repetition Operators and Sequence Composition
Repetition Operators
Methods for Sequences
Sequence Composition
SVA - Knowledge Check - 4
SVA : Miscellaneous Concepts and Connecting Assertions to DUT
Miscellaneous Concepts in SVA
Connecting Assertions to DUT
SVA - Knowledge Check - 5
SVA Labs
SVA Lab Manual - Questasim
SVA Lab Manual - Synopsys VCS
SVA Lab Solution
SVA Case Study
Explanation to Project Specification
Alarm Clock Project Specification
Module Test : SV & SVA
Module Test : SV
Course Instructor
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Sivakumar P R
14 Courses • 267 Students
CEO and Founder, Maven Silicon
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