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Universal Verification Methodology

Discover Universal Verification Methodology with Maven Silicon. Learn the industry-standard techniques for systematic and efficient VLSI verification.

4.8
(40 ratings)
Course Instructor Maven Silicon

₹19900.00 ₹24900.00 20% OFF

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Course Overview

Welcome to the Universal Verification Methodology course – your comprehensive guide to mastering UVM for robust hardware verification. From an overview of UVM to in-depth modules covering UVM TB architecture, factory, stimulus modeling, and much more, this course is designed to equip you with the skills needed for effective verification methodologies. Engage in UVM Labs, create testbench components, and explore the Register Abstraction Layer. Join us on this enlightening journey into the world of Universal Verification Methodology!

Course Curriculum

1 Subject

Universal Verification Methodology

12 Exercises45 Learning Materials

Universal Verification Methodology Overview

UVM_Introduction

Video
43:18

Advanced_UVM_CaseStudies

Video
48:13

Knowledge Check : Introduction to UVM

Exercise

UVM - Quick Reference Guide

UVM - Quick Reference Guide

PDF

UVM TB Architecture and Base Class Hierarchy

UVM Testbench Architecture

Video
13:48

UVM Base Class Hierarchy

Video
14:31

Knowledge Check - UVM TB Architecture and Base Class Hierarchy

Exercise

UVM Factory

UVM Factory - Importance of using factory

Video
11:19

UVM Factory - Registration Process

Video
6:2

UVM Factory - Create Method and Factory Overriding

Video
11:47

Knowledge Check - UVM Factory

Exercise

UVM - Stimulus Modelling & Testbench Overview

UVM Stimulus Modelling - Predefined Methods and Field Registration Process

Video
10:22

UVM Stimulus Modelling - Overriding the predefined do_ methods

Video
10:41

UVM - TB Overview

Video
10:44

Knowledge Check - UVM Stimulus Modelling & TB Overview

Exercise

UVM Phases & Reporting Mechanism

UVM Phases - Necessity of Phases & pre-run Phases

Video
16:27

UVM Phases - Run Phase, post-run Phases and Objection Mechanism

Video
13:13

UVM Reporting Mechanism

Video
15:1

Knowledge Check - UVM Phases & Reporting Mechanism

Exercise

UVM TLM Ports and Configuration

UVM TLM Ports - Blocking put and get ports

Video
11:35

UVM TLM Ports - TLM FIFO and Analysis Ports

Video
13:1

UVM Configuration - Introduction to Configuration Facility

Video
13:2

UVM Configuration - Configuration class and Configuration of Virtual Interface

Video
9:31

Knowledge Check - UVM TLM Ports and Configuration

Exercise

UVM - Creating UVM Testbench Components

Creating UVM TB Components - Sequencers & Drivers

Video
15:1

Creating UVM TB Components - Monitor, Agents, Env and Testcases

Video
16:30

Knowledge Check - UVM - Creating UVM Testbench Components

Exercise

UVM Sequences

UVM Sequences - Introduction and Sequence item flow

Video
11:35

UVM Sequences - Starting the sequences and Default Sequence

Video
15:17

Knowledge Check - UVM Sequences

Exercise

UVM - Virtual Sequences & Virtual Sequencers

UVM Virtual Sequences & Virtual Sequencers - Introduction

Video
13:33

UVM Virtual Sequences & Virtual Sequencers - implementation

Video
8:22

Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers

Exercise

UVM Callbacks & Events

UVM Callbacks

Video
9:23

UVM Events

Video
9:6

Knowledge Check - UVM Callbacks & Events

Exercise

UVM - Creating Scoreboard

UVM Creating Scoreboard

Video
9:20

Knowledge Check - UVM - Creating Scoreboard

Exercise

UVM Lab Setup guide - reference manuals

UVM Labs User Guide

PDF

VPN Configuration Guide

PDF

UVM Labs

Lab1 Solution : Stimulus Modeling

Video
16:2

Lab2 Solution : Factory Overriding

Video
8:19

Lab3 Solution : UVM Phases

Video
10:22

Lab4 Solution : Creating UVM agent

Video
11:44

Lab5 Solution : UVM Sequences

Video
13:22

Lab6 Solution : Virtual Interface

Video
5:50

Lab7 Solution : Agent Integration

Video
8:12

Lab8 Solution : UVM Socreboard

Video
6:39

Lab9 Solution : SoC - UVM VE implementation

Video
8:41

Lab10 Solution : Coverage & Regression

Video
4:33

UVM Lab Manual

PDF

Feedback Form

Feedback Form

External Link

UVM - Register Abstraction Layer

UVM RAL - Intro & Definition of Register Block

Video
15:55

UVM RAL - Adapter, Predictor and Integration

Video
20:36

UVM RAL - Definition of Register Sequences

Video
11:55

Knowledge Check - UVM RAL

Exercise

UVM - CaseStudies

Advanced_UVM_CaseStudies

Video
48:13

Course Instructor

tutor image

Maven Silicon

252 Courses   •   311099 Students


Ratings & Reviews

4.8 /5

40 ratings

28 reviews

5

80%

4

20%

3

0%

2

0%

1

0%
SS
S satyanarayana

6 months ago

SN
SWAPNIL NISHANT

a year ago

SK
Sai Kiran Ratna

a year ago

Good explaination of concepts with examples.

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