VLSI Verification
Optimize your VLSI designs with effective verification at Maven Silicon. Explore proven strategies and methodologies for robust VLSI verification processes.
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Course Overview
Welcome to the VLSI Verification course – your comprehensive journey into mastering verification methodologies in VLSI design. This course covers a range of modules, from introducing the basics to in-depth discussions on SystemVerilog language concepts, memories, interfaces, object-oriented programming, randomization, functional coverage, and more. Engage in case studies involving Dual Port RAM and Maven SoC using SystemVerilog testbenches. Conclude with an overview of the Universal Verification Methodology. Join us on this insightful exploration into the world of VLSI Verification!
Course Curriculum
1 Subject
VLSI Verification
13 Exercises • 51 Learning Materials
Introduction
Getting Familiar with VLSI Verification course
Verification Methodology Overview
Introduction to Verification Methodology
Verification Process
Reusable TB
Verification Environment Architecture
Constraint Random Coverage Driven Verification
Verification Methodologies & Summary
Knowledge Check : Verification Methodology Overview
SystemVerilog Language Concepts
SV Concepts Agenda
SV Overview
SV Transactions
SV Interface
SV Virtual Interface
SV OOP
SV Randomization & Functional Coverage
SV TB Architecture
Knowledge Check : SV language Concepts Overview
SystemVerilog Reference Book - Download FYR
SystemVerilog - Quick Reference Guide
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
SV Data Types - Strings,Packages & Summary
SV Data Types - 2 State, Struct & Enum
Knowledge Check : Data Types
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
SV Memories - Associative Arrays, Array Methods & Summary
SV Memories - Dynamic Arrays & Queues
Knowledge Check:Memories
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
SV Tasks & Functions - Pass by value & ref and Summary
Knowledge Check : Tasks & Functions
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
SV Interfaces - Modports & Clocking Block
SV Interfaces - Examples & Summary
Knowledge Check:Interface & Clocking Block
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
SV OOP - Shallow Vs Deep Copy & Summary
SV OOP - Constructor, Null Object, Object assignments and copy
Knowledge Check: Basic OOP
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
SV OOP - Static properties & methods and Pass by ref
Knowledge Check: Advanced OOP
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
SV Randomization - Set Membership, Constraints & Summary
SV Randomization - Randomize, Pre and Post randomize & Constraints
Knowledge Check: Randomization
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Knowledge Check : Threads , Events, Semaphore & Mailbox
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Knowledge Check : Virtual Interface
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Knowledge Check : Functional Coverage
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Paln
Testbench Architecture and Verification Flow
Transaction and Generator
Interface and Drivers
Monitors
Scoreboard and Reference Model
Environment and Testcases
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Feedback Form
Feedback Form
Universal Verification Methodology Overview
UVM_Introduction
Advanced_UVM_CaseStudies
Knowledge Check : Introduction to UVM
Course Instructor
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Sivakumar P R
14 Courses • 267 Students
CEO and Founder, Maven Silicon
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