Verilog HDL
Equip your team with Verilog HDL proficiency through custom training from Maven Silicon, covering fundamental and advanced applications for effective hardware design.
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Course Overview
Welcome to the Verilog HDL course! Explore modules such as Introduction, Data Types, Operators, Synthesis Coding, and more. Engage in hands-on Verilog Labs, delve into Advanced Verilog concepts, and reinforce learning with Code Coverage Labs. Additional reference materials and a comprehensive Module Test are included for a well-rounded understanding of Verilog HDL.
Course Curriculum
1 Subject
Verilog HDL
12 Exercises • 43 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Introduction to Verilog HDL
Knowledge Check - Introduction to Verilog HDL
Verilog HDL Reference Material
Verilog HDL Reference Book
Verilog HDL - Quick Reference Guide
Data Types
Data Types
Knowledge Check - Data Types
Verilog Operators
Verilog Operators
Knowledge Check - Verilog Operators
Verilog for Verification
Verilog for Verification
Knowledge Check - Verilog for Verification
Assignments
Assignments
Knowledge Check - Assignments
Structured Proceedures
Structured Procedures
Knowledge Check - Structured Procedures
Synthesis Coding Styles
Synthesis Coding Style
Knowledge Check - Synthesis Coding Style
Finite State Machine
Finite State Machine
Knowledge Check - Finite State Machine
Compiler Directive
Compiler Directive
Summary
Verilog HDL Summary
Verilog RTL Coding Examples
Verilog Labs
Verilog Lab Manual
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
Solution to Verilog Lab 01
Solution to Verilog Lab 02
Solution to Verilog Lab 03
Solution to Verilog Lab 04
Solution to Verilog Lab 05
Solution to Verilog Lab 06
Advanced Verilog
Timescale system task & localparm
Generate block & Continuous Procedural Assignments
Self checking testbench and Automatic Tasks
Named Events and Stratified Event Queue
Knowledge Check- Advance Verilog 1
Knowledge Check- Advance Verilog 2
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
Code Coverage
Definition of Code Coverage
Condition & Expression Coverage
Statement and branch coverage
Toggle & FSM Coverage
Questasim commands for Code Coverage
Makefile for Simulations
Knowledge Check-Code Coverage 1
Code Coverage - Reference Book
Code Coverage Reference Book
Advanced Verilog & code Coverage - Labs
Advanced Verilog Lab Solutions Lab 1 & 2
Code Coverage Lab Solutions Lab 3, 4 & 5
Advanced Verilog & Code Coverage Lab Manual - Questasim
Advanced Verilog and Code Coverage Lab Manual - Synopsys VCS
Extra Reference Books
Logic Synthesis using DesignCompiler - Reference Book
Linting using VC Spyglass - Reference Book
Tcl Scripting - Reference Book
Python Scripting - Reference Book
CDC Concepts - Reference Book
Module Test : Verilog HDL
Module test : Verilog
Course Instructor
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Sivakumar P R
16 Courses • 2065 Students
CEO and Founder, Maven Silicon
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