Advanced VLSI Verification
Take on Maven Silicon's Advanced VLSI Verification course to deepen skills in advanced verification methodologies for complex designs.
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Course Overview
Embark on an immersive journey with the Advanced VLSI Verification course, covering a broad spectrum of modules essential for mastering verification methodologies. From in-depth Verilog HDL to advanced SystemVerilog concepts, delve into hands-on labs, tool demos, and case studies. The course concludes with a comprehensive exploration of RISC-V architecture and essential preparation for interviews.
Course Curriculum
5 Subjects
Must Reads
2 Learning Materials
Onboarding & Platform Details
Must Knows
PDF
Admission Form
Admission Form
External Link
Verilog - HDL
8 Exercises • 24 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Verilog_Course_Agenda
Video
00:14:12
VerilogHDL_Introduction
Video
00:28:35
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Advanced Verilog for Verification
Advance Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Summary
Video
00:23:58
Feedback Form
Feedback Form
External Link
Verilog Labs
Instructions - Verilog Labs
PDF
Verilog Lab Manual
PDF
Verilog Labs Folder - Download
ZIP
EDA Tools - Installation Guide
Video
00:18:50
EDA Tools - User Guide
Video
00:05:22
Solution to Lab 1
Video
00:23:43
Solution to Lab 2
Video
00:10:28
Solution to Lab 3
Video
00:06:01
Solution to Lab 4
Video
00:06:53
Solution to Lab 5
Video
00:06:41
Solution to Lab 6
Video
00:08:18
Solutions - Verilog Labs - Download
ZIP
Advanced VLSI Verification
35 Exercises • 169 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Constraint Random Coverage Driven Verification
Video
00:25:37
Verification Methodologies & Summary
Video
00:27:11
Knowledge Check : Verification Methodology Overview
Exercise
Introduction to Linux OS, vi Editor & Simulation Tool
Linux Lab Manual
PDF
Introduction to Linux Operating System
Video
01:15:00
vi Text Editor
Video
00:31:00
Linux Lab 1 : Solution
Video
00:08:26
Linux Lab 2 : Solution
Video
00:05:15
Lab setup
VPN Configuration Guide
PDF
Labs User Guide
PDF
Advanced Verilog
Timescale system task & localparm
Video
00:14:48
Generate block & Continuous Procedural Assignments
Video
00:18:37
Self checking testbench and Automatic Tasks
Video
00:15:34
Knowledge check: Advance verilog 1
Exercise
Named Events and Stratified Event Queue
Video
00:19:56
Knowledge check: Advance verilog 2
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Questasim commands for Code Coverage
Video
00:11:26
Makefile for Simulations
Video
00:08:36
Knowledge check: Code Coverage
Exercise
Code Coverage - Reference Book
Code Coverage - Reference Book
PDF
Advanced Verilog & code Coverage - Labs
Adv. Verilog and Code Coverage Lab User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
00:19:05
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
00:25:16
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Language Concepts
SV Concepts Agenda
Video
00:06:38
SV Overview
Video
00:11:16
SV Transactions
Video
00:14:46
SV Interface
Video
00:14:51
SV Virtual Interface
Video
00:11:40
SV OOP
Video
00:13:56
SV Randomization & Functional Coverage
Video
00:06:47
SV TB Architecture
Video
00:10:19
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
00:10:50
SV Data Types - 2 State, Struct & Enum
Video
00:15:27
SV Data Types - Strings,Packages & Summary
Video
00:09:04
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
00:09:45
SV Memories - Dynamic Arrays & Queues
Video
00:07:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
00:13:19
Knowledge Check : Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
00:11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
00:09:52
Knowledge Check : Tasks&Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
00:18:44
SV Interfaces - Modports & Clocking Block
Video
00:18:30
SV Interfaces - Examples & Summary
Video
00:20:49
Knowledge Check : Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
00:15:05
SV OOP - Constructor, Null Object, Object assignments and copy
Video
00:17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
00:17:30
Knowledge Check : Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
00:20:50
SV OOP - Static properties & methods and Pass by ref
Video
00:15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
00:21:53
Knowledge Check : Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
00:10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
00:12:52
SV Randomization - Set Membership, Constraints & Summary
Video
00:13:22
Knowledge Check : Randomization
Exercise
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Video
00:23:11
Knowledge Check : Threads
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
00:17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
00:15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
00:17:30
Knowledge Check : Functional Coverage
Exercise
SV Lab Setup guide - Reference manuals
VPN Configuration Guide
PDF
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
00:10:14
Verdi Tool Demo - Part-1
Video
00:09:16
Verdi Tool Demo - Part-2
Video
00:07:48
SystemVerilog Labs
Lab 1 Solution : Data Types
Video
00:17:56
Lab 2 Solution : Interfaces
Video
00:09:26
Lab 3 Solution : OOP Basics
Video
00:08:51
Lab 4 Solution : Advanced OOP
Video
00:18:09
Lab 5 Solution : Randomization
Video
00:05:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
00:22:02
Lab 7 Solution : Transaction
Video
00:09:43
Lab 8 Solution : Transactors
Video
00:09:01
Lab 9 Solution : Scoreboard & Reference Model
Video
00:10:59
Lab 10 Solution : Environment & Testcases
Video
00:11:20
SystemVerilog Lab Manual - Questasim
PDF
SystemVerilog Lab Manual - for Synopsys VCS
PDF
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Paln
Video
00:10:18
Testbench Architecture and Verification Flow
Video
00:08:12
Transaction and Generator
Video
00:10:55
Interface and Drivers
Video
00:13:10
Monitors
Video
00:08:56
Scoreboard and Reference Model
Video
00:12:59
Environment and Testcases
Video
00:13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
00:10:45
SystemVerilog Assertions
What are Assertions?
Video
00:13:07
Necessity of using SystemVerilog Assertions
Video
00:14:46
Types of Assertions
Video
00:14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks
Video
00:17:34
System Functions
Video
00:11:48
SVA - Knowledge Check - 2
Exercise
How to write sequences?
Video
00:11:21
Implication Operators
Video
00:24:34
Exercise based on Implication Operators and Timing Windows
Video
00:14:18
SVA - Knowledge Check - 3
Exercise
Repetition Operators
Video
00:21:46
Sequence Composition
Video
00:19:46
Methods for Sequences
Video
00:07:21
SVA - Knowledge Check - 4
Exercise
Miscllenious Cocenpts in SVA
Video
00:07:27
Connecting Assertions to DUT
Video
00:07:59
SVA - Knowledge Check - 5
Exercise
SystemVerilog Assertions - Reference Book
SVA Reference Book
PDF
SVA Case Study
Explanation to Project Specification
Video
00:38:05
Alarm Clock Project Specification
PDF
SystemVerilog Assertions - Labs
SVA Labs User Guide
PDF
SVA Lab Solution
Video
00:12:05
SVA Lab Manual - Questasim
PDF
SVA Lab Manual - Synopsys VCS
PDF
SV & SVA - Module Test
Module Test : SV & SVA
Exercise
Universal Verification Methodology Overview
UVM_Introduction
Video
00:43:18
Advanced_UVM_CaseStudies
Video
00:48:13
Knowledge Check - Universal Verification Methodology Overview
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
00:13:48
UVM Base Class Hierarchy
Video
00:14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
00:11:19
UVM Factory - Registration Process
Video
00:06:02
UVM Factory - Create Method and Factory Overriding
Video
00:11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
00:10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
00:10:41
UVM - TB Overview
Video
00:10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
00:16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
00:13:13
UVM Reporting Mechanism
Video
00:15:01
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
00:11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
00:13:01
UVM Configuration - Introduction to Configuration Facility
Video
00:13:02
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
00:09:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
00:15:01
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
00:16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
00:11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
00:15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
00:13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
00:08:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
00:09:23
UVM Events
Video
00:09:06
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
00:09:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
00:15:55
UVM RAL - Adapter, Predictor and Integration
Video
00:20:36
UVM RAL - Definition of Register Sequences
Video
00:11:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
00:48:13
UVM Labs
Lab1 Solution : Stimulus Modeling
Video
00:16:02
Lab2 Solution : Factory Overriding
Video
00:08:19
Lab3 Solution : UVM Phases
Video
00:10:22
Lab4 Solution : Creating UVM agent
Video
00:11:44
Lab5 Solution : UVM Sequences
Video
00:13:22
Lab6 Solution : Virtual Interface
Video
00:05:50
Lab7 Solution : Agent Integration
Video
00:08:12
Lab8 Solution : UVM Socreboard
Video
00:06:39
Lab9 Solution : SoC - UVM VE implementation
Video
00:08:41
Lab10 Solution : Coverage & Regression
Video
00:04:33
UVM Lab Manual - Questsim
PDF
UVM Lab Manual - Synopsys VCS
PDF
UVM Module Test
Module Test : UVM
Exercise
Gate Level Simulation (GLS)
GLS Flow
PDF
GLS Introduction
Video
00:09:31
SDF Simulation
Video
00:13:02
Test Plan for GLS
Video
00:06:57
GLS Demo
Video
00:10:14
PERL Scripting
PERL Reference Book
PDF
PERL Scripting - Lecture 1
Video
00:48:16
PERL Scripting - Lecture 2
Video
00:41:35
Knowledge check: Perl
Exercise
PERL Labs
Perl Labs User Guide
PDF
PERL Lab Manual
PDF
Lab 01 Solution
Video
00:01:34
Lab 02 Solution
Video
00:01:19
Lab 03 Solution
Video
00:01:59
Lab 04 Solution
Video
00:02:15
Lab 05 Solution
Video
00:02:47
Feedback Form - VMPT
Feedback Form - VMPT
External Link
UVM Pilot Project
Introduction
Video
00:07:06
Project : UVM TB Architecture
Video
00:15:54
Pilot Project Solution
TB Implementation : TB Components - Build & Connect Phases
Video
00:23:50
TB Implementation : TB Components - Run Phases and Testcases for Regression
Video
00:26:11
RISC-V RV32I RTL Design
3 Exercises • 26 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
00:09:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
Project: RISC-V RV32I Multi stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
Interview Preparation
2 Learning Materials
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
00:50:11
Create a winning LinkedIn Profile
How to create a winning LinkedIn profile?
Video
00:37:57
Ratings & Reviews
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FAQ's
1. What is UVM in VLSI?
UVM (Universal Verification Methodology) in VLSI is a standardized framework for verification that provides reusable testbenches and automation for digital design verification. It enables efficient and scalable testing of complex VLSI designs by using SystemVerilog as the base language.
2. How does UVM VLSI verify designs?
UVM VLSI verification involves using the UVM framework to create robust testbenches that verify the functionality, performance, and corner cases of VLSI designs. It helps automate the testing process by offering reusable verification components, making it easier to manage complex verification tasks.
3. What does verification in VLSI involve?
Verification in VLSI involves ensuring that the design behaves as expected by running simulations, checking for bugs, and validating against specifications. It includes functional verification, timing analysis, and integration testing to ensure the integrity of the final chip design.
4. Why is UVM used for VLSI verification?
UVM is used for VLSI verification because it offers a structured approach to building testbenches and ensures reusability, scalability, and maintainability of the verification environment. It enables efficient simulation and debugging of complex VLSI systems, helping to verify designs faster and more thoroughly.
5. What tools are used for VLSI verification?
VLSI verification tools include simulators like ModelSim, VCS, and Questa, which support UVM, as well as formal verification tools, coverage tools, and assertion-based verification methods. These tools help automate the verification process and improve accuracy in detecting errors.
6. What is the role of VLSI design verification?
VLSI design verification ensures that a chip’s design is functional and meets specifications before manufacturing. It involves running simulations, checking the RTL (Register Transfer Level) code, and using verification methodologies like UVM, to find and fix design errors early in the development process.
7. How does UVM help in VLSI design verification?
UVM provides a standardized framework for creating testbenches that automate VLSI design verification. It enables modular test development, reuse of components, and easier management of complex testbenches, which speeds up the verification process and ensures comprehensive coverage.
8. What are the main verification tools used in VLSI?
The main verification tools in VLSI include simulation tools like Cadence Incisive, Synopsys VCS, and Mentor Graphics Questa, along with coverage tools and formal verification tools that support advanced techniques like UVM and assertion-based verification.
9. What is the process of VLSI design verification and testing?
VLSI design verification and testing involve validating the functionality and performance of a VLSI chip through simulations, formal verification, and hardware testing. It ensures that the design meets requirements before manufacturing by using various methodologies like UVM for creating automated tests.
10. What skills are required for a VLSI verification job?
A VLSI verification job requires skills in digital design, knowledge of verification methodologies like UVM, proficiency with verification tools such as ModelSim or VCS, and a good understanding of SystemVerilog. Familiarity with testbenches, assertions, and debugging tools is also essential for success in this field.
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