Advanced VLSI Verification
Take on Maven Silicon's Advanced VLSI Verification course to deepen skills in advanced verification methodologies for complex designs.
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Course Instructor
Maven Silicon
To enroll in this course, please contact the Admin
Course Overview
Embark on an immersive journey with the Advanced VLSI Verification course, covering a broad spectrum of modules essential for mastering verification methodologies. From in-depth Verilog HDL to advanced SystemVerilog concepts, delve into hands-on labs, tool demos, and case studies. The course concludes with a comprehensive exploration of RISC-V architecture and essential preparation for interviews.
Course Curriculum
5 Subjects
Must Reads
2 Learning Materials
Onboarding & Platform Details
Must Knows
PDF
Admission Form
Admission Form
External Link
Verilog - HDL
8 Exercises • 24 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Verilog_Course_Agenda
Video
14:12
VerilogHDL_Introduction
Video
28:35
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
30:4
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
30:6
Knowledge Check - Verilog Operators
Exercise
Advanced Verilog for Verification
Advance Verilog for Verification
Video
29:7
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Summary
Video
23:58
Feedback Form
Feedback Form
External Link
Verilog Labs
Instructions - Verilog Labs
PDF
Verilog Lab Manual
PDF
Verilog Labs Folder - Download
ZIP
EDA Tools - Installation Guide
Video
18:50
EDA Tools - User Guide
Video
5:22
Solution to Lab 1
Video
23:43
Solution to Lab 2
Video
10:28
Solution to Lab 3
Video
6:1
Solution to Lab 4
Video
6:53
Solution to Lab 5
Video
6:41
Solution to Lab 6
Video
8:18
Solutions - Verilog Labs - Download
ZIP
Advanced VLSI Verification
35 Exercises • 169 Learning Materials
Verification Methodology Overview
Introduction to Verification Methodology
Video
22:25
Verification Process
Video
21:46
Reusable TB
Video
7:24
Verification Environment Architecture
Video
19:2
Constraint Random Coverage Driven Verification
Video
25:37
Verification Methodologies & Summary
Video
27:11
Knowledge Check : Verification Methodology Overview
Exercise
Introduction to Linux OS, vi Editor & Simulation Tool
Linux Lab Manual
PDF
Introduction to Linux Operating System
Video
1:15:00
vi Text Editor
Video
31:00
Linux Lab 1 : Solution
Video
8:26
Linux Lab 2 : Solution
Video
5:15
Lab setup
VPN Configuration Guide
PDF
Labs User Guide
PDF
Advanced Verilog
Timescale system task & localparm
Video
14:48
Generate block & Continuous Procedural Assignments
Video
18:37
Self checking testbench and Automatic Tasks
Video
15:34
Knowledge check: Advance verilog 1
Exercise
Named Events and Stratified Event Queue
Video
19:56
Knowledge check: Advance verilog 2
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
6:54
Statement and branch coverage
Video
7:17
Condition & Expression Coverage
Video
7:6
Toggle & FSM Coverage
Video
7:47
Questasim commands for Code Coverage
Video
11:26
Makefile for Simulations
Video
8:36
Knowledge check: Code Coverage
Exercise
Code Coverage - Reference Book
Code Coverage - Reference Book
PDF
Advanced Verilog & code Coverage - Labs
Adv. Verilog and Code Coverage Lab User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
19:5
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
25:16
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Language Concepts
SV Concepts Agenda
Video
6:38
SV Overview
Video
11:16
SV Transactions
Video
14:46
SV Interface
Video
14:51
SV Virtual Interface
Video
11:40
SV OOP
Video
13:56
SV Randomization & Functional Coverage
Video
6:47
SV TB Architecture
Video
10:19
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
10:50
SV Data Types - 2 State, Struct & Enum
Video
15:27
SV Data Types - Strings,Packages & Summary
Video
9:4
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
9:45
SV Memories - Dynamic Arrays & Queues
Video
7:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
13:19
Knowledge Check : Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
9:52
Knowledge Check : Tasks&Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
18:44
SV Interfaces - Modports & Clocking Block
Video
18:30
SV Interfaces - Examples & Summary
Video
20:49
Knowledge Check : Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
15:5
SV OOP - Constructor, Null Object, Object assignments and copy
Video
17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
17:30
Knowledge Check : Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
20:50
SV OOP - Static properties & methods and Pass by ref
Video
15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
21:53
Knowledge Check : Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
12:52
SV Randomization - Set Membership, Constraints & Summary
Video
13:22
Knowledge Check : Randomization
Exercise
SystemVerilog Threads, Mailboxes and Semaphores
SV Threads , Events, Mailbox and Semaphores
Video
23:11
Knowledge Check : Threads
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
17:30
Knowledge Check : Functional Coverage
Exercise
SV Lab Setup guide - Reference manuals
VPN Configuration Guide
PDF
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
10:14
Verdi Tool Demo - Part-1
Video
9:16
Verdi Tool Demo - Part-2
Video
7:48
SystemVerilog Labs
Lab 1 Solution : Data Types
Video
17:56
Lab 2 Solution : Interfaces
Video
9:26
Lab 3 Solution : OOP Basics
Video
8:51
Lab 4 Solution : Advanced OOP
Video
18:9
Lab 5 Solution : Randomization
Video
5:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
22:2
Lab 7 Solution : Transaction
Video
9:43
Lab 8 Solution : Transactors
Video
9:1
Lab 9 Solution : Scoreboard & Reference Model
Video
10:59
Lab 10 Solution : Environment & Testcases
Video
11:20
SystemVerilog Lab Manual - Questasim
PDF
SystemVerilog Lab Manual - for Synopsys VCS
PDF
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Paln
Video
10:18
Testbench Architecture and Verification Flow
Video
8:12
Transaction and Generator
Video
10:55
Interface and Drivers
Video
13:10
Monitors
Video
8:56
Scoreboard and Reference Model
Video
12:59
Environment and Testcases
Video
13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
10:45
SystemVerilog Assertions
What are Assertions?
Video
13:7
Necessity of using SystemVerilog Assertions
Video
14:46
Types of Assertions
Video
14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks
Video
17:34
System Functions
Video
11:48
SVA - Knowledge Check - 2
Exercise
How to write sequences?
Video
11:21
Implication Operators
Video
24:34
Exercise based on Implication Operators and Timing Windows
Video
14:18
SVA - Knowledge Check - 3
Exercise
Repetition Operators
Video
21:46
Sequence Composition
Video
19:46
Methods for Sequences
Video
7:21
SVA - Knowledge Check - 4
Exercise
Miscllenious Cocenpts in SVA
Video
7:27
Connecting Assertions to DUT
Video
7:59
SVA - Knowledge Check - 5
Exercise
SystemVerilog Assertions - Reference Book
SVA Reference Book
PDF
SVA Case Study
Explanation to Project Specification
Video
38:5
Alarm Clock Project Specification
PDF
SystemVerilog Assertions - Labs
SVA Labs User Guide
PDF
SVA Lab Solution
Video
12:5
SVA Lab Manual - Questasim
PDF
SVA Lab Manual - Synopsys VCS
PDF
SV & SVA - Module Test
Module Test : SV & SVA
Exercise
Universal Verification Methodology Overview
UVM_Introduction
Video
43:18
Advanced_UVM_CaseStudies
Video
48:13
Knowledge Check - Universal Verification Methodology Overview
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
13:48
UVM Base Class Hierarchy
Video
14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
11:19
UVM Factory - Registration Process
Video
6:2
UVM Factory - Create Method and Factory Overriding
Video
11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
10:41
UVM - TB Overview
Video
10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
13:13
UVM Reporting Mechanism
Video
15:1
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
13:1
UVM Configuration - Introduction to Configuration Facility
Video
13:2
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
9:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
15:1
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
8:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
9:23
UVM Events
Video
9:6
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
9:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
15:55
UVM RAL - Adapter, Predictor and Integration
Video
20:36
UVM RAL - Definition of Register Sequences
Video
11:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
48:13
UVM Labs
Lab1 Solution : Stimulus Modeling
Video
16:2
Lab2 Solution : Factory Overriding
Video
8:19
Lab3 Solution : UVM Phases
Video
10:22
Lab4 Solution : Creating UVM agent
Video
11:44
Lab5 Solution : UVM Sequences
Video
13:22
Lab6 Solution : Virtual Interface
Video
5:50
Lab7 Solution : Agent Integration
Video
8:12
Lab8 Solution : UVM Socreboard
Video
6:39
Lab9 Solution : SoC - UVM VE implementation
Video
8:41
Lab10 Solution : Coverage & Regression
Video
4:33
UVM Lab Manual - Questsim
PDF
UVM Lab Manual - Synopsys VCS
PDF
UVM Module Test
Module Test : UVM
Exercise
Gate Level Simulation (GLS)
GLS Flow
PDF
GLS Introduction
Video
9:31
SDF Simulation
Video
13:2
Test Plan for GLS
Video
6:57
GLS Demo
Video
10:14
PERL Scripting
PERL Reference Book
PDF
PERL Scripting - Lecture 1
Video
48:16
PERL Scripting - Lecture 2
Video
41:35
Knowledge check: Perl
Exercise
PERL Labs
Perl Labs User Guide
PDF
PERL Lab Manual
PDF
Lab 01 Solution
Video
1:34
Lab 02 Solution
Video
1:19
Lab 03 Solution
Video
1:59
Lab 04 Solution
Video
2:15
Lab 05 Solution
Video
2:47
Feedback Form - VMPT
Feedback Form - VMPT
External Link
UVM Pilot Project
Introduction
Video
7:6
Project : UVM TB Architecture
Video
15:54
Pilot Project Solution
TB Implementation : TB Components - Build & Connect Phases
Video
23:50
TB Implementation : TB Components - Run Phases and Testcases for Regression
Video
26:11
RISC-V RV32I RTL Design
3 Exercises • 26 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
9:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
9:15
RISC-V ISA Part-1 ( introduction)
Video
10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
20:42
Base ISA
Video
15:6
RV32I Base Instructions(R & I type)
Video
23:9
RV32I Base Instructions(S & B Type)
Video
23:30
RV32I Base Instructions(J Type)
Video
15:19
RV32I Base Instructions (U type)
Video
17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
8:36
RISC-V Register File and RV32I Instructions Format
Video
12:52
RV32I R Type ALU Datapath
Video
9:29
RV32I I Type ALU Datapath
Video
6:33
RV32I S Type ALU Datapath - Load & Store
Video
13:4
RV32I B Type ALU Datapath
Video
8:23
RV32I J Type ALU Datapath JAL & JALR
Video
9:26
RV32I U Type ALU Datapath and Summary
Video
10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
16:3
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
Project: RISC-V RV32I Multi stage pipeline processor RTL Design
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
Interview Preparation
2 Learning Materials
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
50:11
Create a winning LinkedIn Profile
How to create a winning LinkedIn profile?
Video
37:57
Ratings & Reviews
4.7 /5
214 ratings
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Course Instructor
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Maven Silicon
252 Courses • 309885 Students
FAQ's
1. What is UVM in VLSI?
UVM (Universal Verification Methodology) in VLSI is a standardized framework for verification that provides reusable testbenches and automation for digital design verification. It enables efficient and scalable testing of complex VLSI designs by using SystemVerilog as the base language.
2. How does UVM VLSI verify designs?
UVM VLSI verification involves using the UVM framework to create robust testbenches that verify the functionality, performance, and corner cases of VLSI designs. It helps automate the testing process by offering reusable verification components, making it easier to manage complex verification tasks.
3. What does verification in VLSI involve?
Verification in VLSI involves ensuring that the design behaves as expected by running simulations, checking for bugs, and validating against specifications. It includes functional verification, timing analysis, and integration testing to ensure the integrity of the final chip design.
4. Why is UVM used for VLSI verification?
UVM is used for VLSI verification because it offers a structured approach to building testbenches and ensures reusability, scalability, and maintainability of the verification environment. It enables efficient simulation and debugging of complex VLSI systems, helping to verify designs faster and more thoroughly.
5. What tools are used for VLSI verification?
VLSI verification tools include simulators like ModelSim, VCS, and Questa, which support UVM, as well as formal verification tools, coverage tools, and assertion-based verification methods. These tools help automate the verification process and improve accuracy in detecting errors.
6. What is the role of VLSI design verification?
VLSI design verification ensures that a chip’s design is functional and meets specifications before manufacturing. It involves running simulations, checking the RTL (Register Transfer Level) code, and using verification methodologies like UVM, to find and fix design errors early in the development process.
7. How does UVM help in VLSI design verification?
UVM provides a standardized framework for creating testbenches that automate VLSI design verification. It enables modular test development, reuse of components, and easier management of complex testbenches, which speeds up the verification process and ensures comprehensive coverage.
8. What are the main verification tools used in VLSI?
The main verification tools in VLSI include simulation tools like Cadence Incisive, Synopsys VCS, and Mentor Graphics Questa, along with coverage tools and formal verification tools that support advanced techniques like UVM and assertion-based verification.
9. What is the process of VLSI design verification and testing?
VLSI design verification and testing involve validating the functionality and performance of a VLSI chip through simulations, formal verification, and hardware testing. It ensures that the design meets requirements before manufacturing by using various methodologies like UVM for creating automated tests.
10. What skills are required for a VLSI verification job?
A VLSI verification job requires skills in digital design, knowledge of verification methodologies like UVM, proficiency with verification tools such as ModelSim or VCS, and a good understanding of SystemVerilog. Familiarity with testbenches, assertions, and debugging tools is also essential for success in this field.
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