VLSI Physical Design Internship
Explore VLSI Physical Design Internship opportunities at Maven Silicon for hands-on expertise in real-world projects.
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Course Overview
Embark on the Physical Design Internship, a comprehensive program guiding you through the intricacies of VLSI physical design. From Linux basics to detailed exercises in Placement, DFT, Floorplanning, Routing, Synthesis, and PDKs, gain practical insights. Conclude with an exploration of Timing Constraints, a module test, and a broad overview of Physical Design.
Course Curriculum
10 Subjects
Must Read - Internship Course
5 Learning Materials
Must Knows
Must Knows
PDF
How to navigate elearn platform?
External Link
How to raise a ticket for all non-technical queries?
External Link
How to ask a question for technical doubts?
External Link
Admission Form
Admission Form
External Link
Verilog HDL Theory & Labs
8 Exercises • 22 Learning Materials
Introduction to Verilog HDL
Setting Expectations - Course Agenda
Video
00:12:01
Introduction to Verilog HDL
Video
00:23:59
Knowledge Check - Introduction to Verilog HDL
Exercise
Verilog HDL Reference Material
Verilog HDL Reference Book
PDF
Verilog HDL - Quick Reference Guide
PDF
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Proceedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Styles
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Verilog Lab Manual
PDF
Verilog Lab Manual - Synopsys VCS, Verdi and DesignCompiler
PDF
Solution to Verilog Lab 01
Video
00:22:02
Solution to Verilog Lab 02
Video
00:17:12
Solution to Verilog Lab 03
Video
00:11:57
Solution to Verilog Lab 04
Video
00:16:04
Solution to Verilog Lab 05
Video
00:19:10
Solution to Verilog Lab 06
Video
00:16:25
Physical Design Foundation
2 Exercises • 19 Learning Materials
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
Feedback Form
Feedback Form
External Link
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
Introduction to Physical Design
Intro to VLSI
Video
00:06:19
Design Styles
Video
00:09:36
Partitioning
Video
00:05:12
Floor-planning
Video
00:05:34
placement
Video
00:05:34
CTS
Video
00:06:35
Routing
Video
00:04:21
Static Timing Analysis (STA)
Video
00:05:24
Knowledge Check : Introduction to PD
Exercise
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Foundation - Design for Testability
1 Exercises • 9 Learning Materials
DFT Basics
Introduction to DFT
Video
00:11:15
Basic Testing Principles
Video
00:11:39
Feedback Form
External Link
Fault Collapsing
Video
00:12:27
What is DFT?
Video
00:10:50
DFT Techniques- Structured Techniques
Video
00:09:15
Knowledge check: DFT techniques
Exercise
Project - Demo
Introduction_dft_structured_techniques
Video
00:01:02
Scan_chain_insertion
Video
00:07:43
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
Static Timing Analysis
1 Exercises • 15 Learning Materials
Static Timing Analysis
Why & What is Timing Analysis?
Video
00:07:40
Types of Timing Analysis
Video
00:10:22
False Paths & Multi Cycle Paths
Video
00:19:36
STA in Design Flow
Video
00:05:24
Clock - Part -1
Video
00:17:35
Clock - Part - 2
Video
00:17:41
Timing Parameters in STA - Part-1
Video
00:15:49
Timing Parameters in STA - Part-2
Video
00:13:58
Feedback Form
External Link
Timing Parameters in STA - Part-3
Video
00:10:24
Timing Analysis on Sequential Circuits - Part-1
Video
00:18:30
Timing Analysis on Sequential Circuits - Part-2
Video
00:12:48
STA Proceedure
Video
00:10:27
Different Techniques to improve timing
Video
00:12:51
Knowledge Check : STA
Exercise
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
VLSI - Physical Design - Floorplanning - V1
2 Exercises • 14 Learning Materials
Floorplanning
What is Floorplanning
Video
00:04:37
Die Size Estimation and Utilization
Video
00:02:45
Aspect Ratio
Video
00:04:28
Initialize Floorplanning
Video
00:01:52
Macros
Video
00:03:39
Good and Bad Floorplan
Video
00:03:20
Placement Blockages
Video
00:03:46
Guidelines for Good Floorplan
Video
00:01:43
Knowledge Check : Floorplan
Exercise
Reference Book : Floorplanning
Ref: FloorPlanning
PDF
Powerplanning
Powerplanning Introduction
Video
00:05:05
Power Network Synthesis
Video
00:10:40
Running PNS
Video
00:05:04
Power Calculations
Video
00:02:48
Reference Book : Powerplanning
Power Planning
PDF
Knowledge Check : Powerplanning
Knowledge Check : Powerplanning
Exercise
VLSI - Physical Design - Placement - V1
1 Exercises • 8 Learning Materials
Placement
Introduction to Placement
Video
00:04:14
Placement Flow
Video
00:07:10
Routing Resources and Congestion
Video
00:04:30
Timing Vs Congestion Driven Placement
Video
00:05:47
Floorplan settings to reduce congestion
Video
00:02:26
HFNS Gate Sizing and Cloning Scan chain Reordering
Video
00:03:55
Knowledge Check : Placement
Exercise
Reference Book : Placement
Placement
PDF
Physical Only Cells
PDF
VLSI - Physical Design - Routing - V1
2 Exercises • 4 Learning Materials
Routing
Routing
Video
00:02:16
Routing Flow
Video
00:03:37
Metal Layer Stacks
Video
00:01:57
Knowledge Check: routing
Exercise
Reference Book : Routing
Routing
PDF
Module Test 3: Floorplanning, Powerplanning, Placement, CTS, Routing
Module test 3: Floorplanning, Powerplan, Placement, CTS, Routing
Exercise
Foundation - Physical Verification
8 Learning Materials
Physical Verification DRC and LVS
PD_Physical_Verification_DRC_and_LVS
Video
00:48:33
PD_Physical_Verification_Calibre_tool_Introduction
Video
01:06:07
Feedback Form
External Link
PV
Video
00:04:05
PERC
Introduction to Calibre PERC
Video
00:44:38
PERC: Nets, Paths
Video
00:48:42
Calibre PERC - Net Coding Basics
Video
00:25:51
Feedback Form - Overall Experience
Feedback Form - Overall Experience
External Link
SPI PD Implementation Using QFlow
1 Exercises • 9 Learning Materials
Q-Flow
Q-Flow Installation Guide
PDF
Physical Design Implementation of SPI using Qflow
PDF
Synthesis Using Yosys Tool
PDF
EDA Tools User Guide
Must read Instruction manual
PDF
Virtualbox_Ubuntu - Installation Guide
Video
00:20:17
Installation guide for Virtual Box and Ubuntu in Windows
PDF
Verilog RTL code of SPI Protocol
ZIP
SPI top
ZIP
Feedback Form - PD Internship
Feedback Form - PD Internship
External Link
Final Test : Physical Design Internship
Final Test : Physical Design Internship
Exercise
Course Instructor
Ratings & Reviews
4.5 /5
22 ratings
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FAQ's
1. What is a VLSI physical design internship program?
A VLSI physical design internship program offers students or fresh graduates hands-on experience in physical design aspects of VLSI (Very Large Scale Integration). It involves working with design tools and techniques related to layout, placement, routing, and verification. Interns learn how to optimize designs for performance, area, and power while understanding the physical constraints and challenges involved in chip design.
2. Who is eligible for the VLSI physical design internship program?
The VLSI physical design internship program is open to engineering students or graduates with a background in VLSI design, electrical engineering, or related fields. A basic understanding of digital design, knowledge of tools like Cadence or Synopsys, and interest in semiconductor design are essential for eligibility.
3. What skills will I gain from the physical design internship program?
During the internship, you will gain skills in physical design flow, including RTL-to-GDSII, floorplanning, placement, clock tree synthesis, routing, and verification. You will also work with industry-standard tools for design and verification and learn how to manage physical constraints like power, area, and signal integrity.
4. Is the physical design internship available online?
Yes, some institutions and companies offer online physical design internships, allowing you to work remotely while gaining valuable experience. These programs typically involve virtual sessions, tool access, and collaborative projects, providing flexibility for students worldwide.
5. Can I receive certification after completing the physical design internship?
Many VLSI physical design internship programs offer certification upon successful completion. The certification can add value to your resume and showcase your proficiency in VLSI physical design and related areas.
6. What is a Physical Design Internship with Certification?
A Physical Design Internship with Certification is an internship program where, upon successful completion, interns receive a certification that validates their knowledge and practical experience in physical design for VLSI circuits, making them more competitive in the job market.
7. What is an Internship for VLSI Physical Design Students?
An Internship for VLSI Physical Design Students provides practical exposure to various physical design processes in VLSI, such as floorplanning, clock tree synthesis, place-and-route, and layout optimization, offering students a real-world experience in the field.
8. What is an Advanced Physical Design Internship?
An Advanced Physical Design Internship focuses on complex topics in VLSI physical design, such as advanced routing techniques, power grid optimization, 3D IC design, and performance analysis.
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