Advanced VLSI Design & Verification
Start learning VLSI Design and Verification, from anytime, anywhere - a complete self-paced online learning course
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Course Overview
This is a self paced course which caters learning on VLSI Design and Verification. This course provides a comprehensive journey into mastering the essentials of VLSI from Digital Electronics to Verilog HDL and also aims in providing an indepth knowledge in Advanced VLSI verification concepts, covering a broad spectrum of modules essential for mastering in verification methodologies.
The course covers a range of modules designed to equip you with the skills needed for effective VLSI design and verification offering hands-on activities like labs, tool demos, projects, case studies and assignments to reinforce your knowledge and emerge ready to tackle VLSI challenges. The course includes a comprehensive exploration of RISC-V architecture and essential preparation for interview
Course Curriculum
21 Subjects
Semiconductor Industry
1 Exercises • 4 Learning Materials
Why Semiconductors?
Why Semiconductors?
Video
00:10:53
Semiconductor Supply Chain
Semiconductor Supply CHain
Video
00:12:31
Semiconductor Ecosystem
Semiconductor Ecosystem
Video
00:13:34
AI-driven Semiconductor Industry
AI-Driven
Video
00:07:21
Knowledge Check
Knowledge Check - Semiconductor Industry
Exercise
Must Read -Advanced VLSI Design and Verification - Online
2 Learning Materials
Onboarding Details & Day Planner
Must knows
PDF
Day Planner
PDF
VLSI - Design - Introduction to VLSI
1 Exercises • 9 Learning Materials
Introduction to VLSI & SoC Design
Electronic System
Video
00:26:43
Smartphone - SoC - Architecture
Video
00:09:55
SoC Design
Video
00:16:59
ASIC Vs FPGA
Video
00:12:07
Knowledge Check : Introduction to VLSI
Exercise
ASIC Design Flow
ASIC Design Flow - Part-1 (Specification)
Video
00:13:04
ASIC Design Flow - Part-2 (Architecture to RTL Design)
Video
00:09:32
ASIC Design Flow - Part-3 (Verification to Gate Level Simulation)
Video
00:09:05
ASIC Design Flow - Part-4 (DFT to STA)
Video
00:10:07
ASIC Design Flow - Part-5 (Layout to GDS - II and AMS Flow)
Video
00:14:03
VLSI - Design -Advanced Digital Design
23 Exercises • 44 Learning Materials
Introduction To Digital Electronics
Introduction to Digital Electronics
Video
00:13:26
Number System and Codes
Introduction to Number Systems and Codes
Video
00:37:45
Number Systems
Video
00:27:09
Codes
Video
00:10:09
Assignment 1 - Number Systems & Codes
PDF
Submit your Digital Assignment - 1
Assignment
Solution to Assignment 1 - Number Systems & Codes
Video
01:01:52
Knowledge Check : Number Systems and Codes
Exercise
Logic Circuits
Logic Circuits
Video
00:55:07
Knowledge Check : Logic Circuits and Boolean Algebra-1
Exercise
Boolean Algebra & Logic Gates
Video
00:50:14
Knowledge Check : Logic Circuits and Boolean Algebra-2
Exercise
Assignment 2 - Boolean Algebra & Logic Gates
PDF
Submit your Digital Assignment -2
Assignment
Solution to Assignment 2 - Boolean Algebra & Logic Gates
Video
01:40:17
Combinational Circuits - Basics
Combinational Circuits - I
Video
00:28:25
Knowledge Check : Combinational Circuits - Basics- I
Exercise
Combinational Circuits - II
Video
00:44:08
Knowledge Check : Combinational Circuits - Basics-2
Exercise
Combinational Logic Circuits - Advanced
Combinational Logic Circuits
Video
00:21:08
Combinational Logic Circuits - Delays
Video
00:09:11
Encoders, decoders and Magnitude Comparators
Video
00:11:41
Multiplexers and Demultiplexers
Video
00:18:58
Universal Logic Gates and Tristate Buffers
Video
00:08:37
Summary & Knowledge Check
Video
00:25:42
Solution to Assignment 3 - Combinational Logic Circuits
Video
01:35:39
Assignment 3 - Combinational Logic Circuits
PDF
Submit your Digital Assignment -3
Assignment
Knowledge Check : Combinational Circuits - Advanced-1
Exercise
Sequential Circuits - Basics
Sequential Circuits - I
Video
00:40:58
Knowledge Check : Sequential Circuits Basics -1
Exercise
Sequential Circuits - II
Video
00:45:15
Knowledge Check : Sequential Circuits Basics-2
Exercise
Sequential Circuits - Advanced
Sequential Circuits - Latches & Flipflops
Video
00:25:19
Flipflops - Excitation Tables and Conversion Techniques
Video
00:13:16
Assignment - 4 Latches & Flipflops
PDF
Submit your Digital Assignment - 4
Assignment
Solution to Assignment - 4 Latches & Flipflops
Video
01:00:12
Knowledge Check : Sequential Circuits : Advanced -1
Exercise
Registers & Counters
Video
00:37:19
Sequence Generators & Frequency dividers
Video
00:26:02
Assignment - 5 Registers & Counters
PDF
Submit your Digital Assignment -5
Assignment
Solution to Assignment - 5
Video
01:13:02
Knowledge Check : Sequential Circuits : Advanced -2
Exercise
Finite State Machine FSM - Basics
FSM
Video
00:37:39
Knowledge Check : FSM - Basic
Exercise
FSM - Advanced
Finite State Machines - Part - 1
Video
00:27:44
Finite State Machines - Part - 2
Video
00:21:43
Assignment - 6 Finite State Machines
PDF
Submit your Digital Assignment -6
Assignment
Solution to Assignment - 6
Video
01:01:05
Knowledge Check : Finite State Machines - Advanced
Exercise
Memories
Memories
Video
00:25:54
Knowledge Check :Memories -1
Exercise
Memories & PLD
Video
00:29:45
Assignment - 7 Memories, FIFO, Glitches & PLD
PDF
Submit your Digital Assignment -7
Assignment
Solution to Assignment - 7
Video
00:21:50
Knowledge Check : Memories, Glitches and PLD)
Exercise
Digital Design Reference Book - Download FYR
Digital Design Reference Book
PDF
Advanced Digital Reference Book
PDF
Feedback Form - Digital
Feedback form - Trainer
feedback_form
Feeback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
Digital Module Test
Module Test : Digital
Exercise
Digital Module Test [ PD ]
Module Test : Digital
Exercise
VLSI - Design -Static Timing Analysis
5 Exercises • 13 Learning Materials
STA : Introduction
Why & What is Timing Analysis?
Video
00:07:40
Types of Timing Analysis
Video
00:10:22
False Paths & Multi Cycle Paths
Video
00:19:36
STA in Design Flow
Video
00:05:24
Knowledge Check : Introduction to STA
Exercise
STA: Clock
Clock - Part -1
Video
00:17:35
Clock - Part - 2
Video
00:17:41
Knowledge Check - Clock
Exercise
STA : Timing Parameters
Timing Parameters in STA - Part-1
Video
00:15:49
Timing Parameters in STA - Part-2
Video
00:13:58
Timing Parameters in STA - Part-3
Video
00:10:24
Knowledge Check - Timing Parameters
Exercise
STA : Timing Analysis Procedure
Timing Analysis on Sequential Circuits - Part-1
Video
00:18:30
Timing Analysis on Sequential Circuits - Part-2
Video
00:12:48
STA Procedure
Video
00:10:27
Knowledge Check - Timing analysis Procedure
Exercise
STA - Techniques to Improve Timing
Different Techniques to improve timing
Video
00:12:51
Knowledge Check - Techniques to Improve Timing
Exercise
VLSI - Design - Linux , Labs and VPN
2 Exercises • 7 Learning Materials
Introduction to Linux Operating System & vi Text Editor
Introduction to Linux Operating System
Video
01:15:00
vi Text Editor
Video
00:31:00
Knowledge check: Linux
Exercise
Labs User Guide & VPN Configuration Guide
Linux Labs User Guide
PDF
VPN_Configuration_Guide
PDF
Linux Lab Manual
PDF
Linux Lab 1 : Solution
Video
00:08:26
Linux Lab 2 : Solution
Video
00:05:15
Module test
Module Test : M4 - Linux
Exercise
VLSI - Design -Verilog HDL
10 Exercises • 55 Learning Materials
Verilog HDL Reference Material
Verilog HDL - Quick Reference Guide
PDF
Introduction to Verilog HDL
Verilog_Course_Agenda
Video
00:14:12
VerilogHDL_Introduction
Video
00:28:35
Knowledge Check - Introduction to Verilog HDL
Exercise
Data Types
Data Types
Video
00:30:04
Knowledge Check - Data Types
Exercise
Verilog Operators
Verilog Operators
Video
00:30:06
Knowledge Check - Verilog Operators
Exercise
Verilog for Verification
Verilog for Verification
Video
00:29:07
Knowledge Check - Verilog for Verification
Exercise
Compiler Directive
Compiler Directive
Video
00:17:27
Assignments
Assignments
Video
00:23:21
Knowledge Check - Assignments
Exercise
Structured Procedures
Structured Procedures
Video
00:20:31
Knowledge Check - Structured Procedures
Exercise
Synthesis Coding Style
Synthesis Coding Style
Video
00:20:59
Knowledge Check - Synthesis Coding Style
Exercise
Finite State Machine
Finite State Machine
Video
00:16:19
Knowledge Check - Finite State Machine
Exercise
Summary
Verilog HDL Summary
Video
00:23:58
Verilog RTL Coding Examples
Video
00:28:40
Verilog Labs
Must read Instruction manual
PDF
Instructions - Verilog Labs
PDF
EDA Tools - Installation Guide
Video
00:18:50
VirtualBox_Ubuntu_Installation_on_windows
PDF
Xilinx ISE Installation Guide
PDF
Xilinx_Installation_video
Video
00:20:16
Verilog Labs
ZIP
EDA Tools - User Guide
Video
00:05:22
Solution to Lab1
Video
00:22:02
Solution to Lab 2
Video
00:17:12
Solution to Lab 3
Video
00:11:57
Solution to Lab 4
Video
00:06:53
Solution to Lab 5
Video
00:06:41
Solution to Lab 6
Video
00:08:18
Verilog_lab_manual_modelsim_quartus
PDF
Verilog Assignments
Verilog Assignment - 1
PDF
Solution to Verilog Assignment - 1
Video
00:10:08
Verilog Assignment - 2
PDF
Solution to Verilog Assignment - 2
Video
00:08:13
Verilog Assignment - 3
PDF
Solution to Verilog Assignment - 3
Video
00:11:57
Verilog Assignment - 4
PDF
Solution to Verilog Assignment - 4
Video
00:15:14
Assignment - 5 Structured Procedures
PDF
Solution to Verilog Assignment 5
Video
00:10:16
Assignment - 6 Finite state machines
PDF
Solution to Verilog Assignment 6
Video
00:11:58
Extra Reference Books
Linting using VC Spyglass - Reference Book
PDF
Logic Synthesis using DesignCompiler - Reference Book
PDF
Feedback Form - Verilog Theory and Labs
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feeback form - Infrastructure
feedback_form
Verilog - Module test
Verilog Module Test
Exercise
Router 1x3 RTL design
Router_1x3_design - Specification
PDF
Introduction to Router
Video
00:10:53
Router Top Packet Structure
Video
00:07:16
Input Output Protocol
Video
00:04:40
Router RTL Design & Linting Report Submission
Assignment
Feedback Form - Router Design
External Link
Router Architecture
Video
00:19:17
VLSI - Design - Advanced Verilog&Code Coverage
5 Exercises • 17 Learning Materials
Advanced Verilog
Timescale system task & localparm
Video
00:14:48
Generate block & Continuous Procedural Assignments
Video
00:18:37
Knowledge Check- Advance Verilog 1
Exercise
Self checking testbench and Automatic Tasks
Video
00:15:34
Named Events and Stratified Event Queue
Video
00:19:56
Knowledge Check- Advance Verilog 2
Exercise
Knowledge Check : Design Compiler
Exercise
Knowledge Check: RTL Linting
Exercise
Advanced Verilog Reference Book
Advanced Verilog - Reference Book
PDF
Code Coverage
Definition of Code Coverage
Video
00:06:54
Statement and branch coverage
Video
00:07:17
Condition & Expression Coverage
Video
00:07:06
Toggle & FSM Coverage
Video
00:07:47
Questasim commands for Code Coverage
Video
00:11:26
Makefile for Simulations
Video
00:08:36
Knowledge Check-Code Coverage 1
Exercise
Code Coverage - Reference Book
Code Coverage Reference Book
PDF
Advanced Verilog & Code Coverage Labs
Adv. Verilog and Code Coverage Labs User Guide
PDF
Advanced Verilog & Code Coverage Lab Manual - Questasim
PDF
Advanced Verilog Lab Solutions Lab 1 & 2
Video
00:19:05
Code Coverage Lab Solutions Lab 3, 4 & 5
Video
00:25:16
Router Project - Specification
Router_1x3_design - Specification
PDF
VLSI - Design - FPGA Architecture
2 Exercises • 2 Learning Materials
FPGA Architecture
FPGA - Lecture 1
Video
00:25:40
Knowledge Check - FPGA 1
Exercise
FPGA - Lecture 2
Video
00:28:10
Knowledge Check - FPGA 2
Exercise
VLSI - Design -CMOS Fundamentals
2 Exercises • 4 Learning Materials
CMOS Fundamentals
CMOS - Lecture 1
Video
00:30:50
CMOS - Lecture 2
Video
00:33:46
CMOS - Lecture 3
Video
00:23:45
CMOS Reference Book
CMOS Reference Book
PDF
Knowledge Check - CMOS
Knowledge Check - CMOS
Exercise
Module Test : CMOS
Knowledge Check - CMOS
Exercise
VLSI - Design -RISC-V
3 Exercises • 23 Learning Materials
RISC-V Instruction Set Architecture
RISC-V Overview
Video
00:09:42
RISC-V Open ISA Part-1 - (Introduction to Various ISA's and Extensions of RISC-V)
Video
00:12:17
RISC-V Open ISA Part-2 (SoC architecture based on RISC-V ISA)
Video
00:09:15
RISC-V ISA Part-1 ( introduction)
Video
00:10:43
RISC-V ISA Part-2 ( RISC-V Registers and Modes)
Video
00:15:58
RISC-V ISA Part-3 ( introduction to Privileged Architecture)
Video
00:20:42
Base ISA
Video
00:15:06
RV32I Base Instructions(R & I type)
Video
00:23:09
RV32I Base Instructions(S & B Type)
Video
00:23:30
RV32I Base Instructions(J Type)
Video
00:15:19
RV32I Base Instructions (U type)
Video
00:17:11
Knowledge Check : RISC-V ISA
Exercise
RISC-V RV32I RTL Architecture Design
RISC-V Execution Stages and Flow
Video
00:08:36
RISC-V Register File and RV32I Instructions Format
Video
00:12:52
RV32I R Type ALU Datapath
Video
00:09:29
RV32I I Type ALU Datapath
Video
00:06:33
RV32I S Type ALU Datapath - Load & Store
Video
00:13:04
RV32I B Type ALU Datapath
Video
00:08:23
RV32I J Type ALU Datapath JAL & JALR
Video
00:09:26
RV32I U Type ALU Datapath and Summary
Video
00:10:18
Knowledge Check : RISC-V RTL Design
Exercise
RISC-V RV32I 5 Stage Pipelined RTL Design
CPU Performance and RISC-V 5 Stage Pipeline Overview
Video
00:15:12
RISC-V 5 Stage Pipeline Data Hazards & Design Approach
Video
00:16:03
RISC-V 5 Stage Pipeline Control Hazards & Design Approach
Video
00:13:51
Knowledge Check : RISC-V Pipelined RTL Design
Exercise
RISC-V RV32I Reference Guide
RISC-V RV32I Quick Reference Guide
PDF
VLSI - Verification -ASIC Verification Methodologies
1 Exercises • 6 Learning Materials
ASIC Verification Methodology Overview
Introduction to Verification Methodology
Video
00:22:25
Verification Process
Video
00:21:46
Reusable TB
Video
00:07:24
Verification Environment Architecture
Video
00:19:02
Constraint Random Coverage Driven Verification
Video
00:25:37
Verification Methodologies & Summary
Video
00:27:11
Knowledge Check : Verification Methodology Overview
Exercise
VLSI - Verification -SystemVerilog HVL
12 Exercises • 73 Learning Materials
SystemVerilog Language Concepts
SV Concepts Agenda
Video
00:06:38
SV Overview
Video
00:11:16
SV Transactions
Video
00:14:46
SV Interface
Video
00:14:51
SV Virtual Interface
Video
00:11:40
SV OOP
Video
00:13:56
SV Randomization & Functional Coverage
Video
00:06:47
SV TB Architecture
Video
00:10:19
Knowledge Check : SV language Concepts Overview
Exercise
SystemVerilog Reference Book
SystemVerilog - Quick Reference Guide
PDF
SystemVerilog Datatypes
SystemVerilog Introduction & Logic Data Type
Video
00:10:50
SV Data Types - 2 State, Struct & Enum
Video
00:15:27
SV Data Types - Strings,Packages & Summary
Video
00:09:04
Knowledge Check : Data Types
Exercise
SystemVerilog Memories
SV Memories - Introduction, Packed and Multi Dimensional Arrays
Video
00:09:45
SV Memories - Dynamic Arrays & Queues
Video
00:07:41
SV Memories - Associative Arrays, Array Methods & Summary
Video
00:13:19
Knowledge Check:Memories
Exercise
SystemVerilog Tasks & Functions
SV Tasks & Functions - Introduction, Void Functions, Fun return & Automatic Task
Video
00:11:32
SV Tasks & Functions - Pass by value & ref and Summary
Video
00:09:52
Knowledge Check : Tasks & Functions
Exercise
SystemVerilog Interfaces
SV Interfaces - Introduction & Verilog ports Vs SV Interface
Video
00:18:44
SV Interfaces - Modports & Clocking Block
Video
00:18:30
SV Interfaces - Examples & Summary
Video
00:20:49
Knowledge Check:Interface & Clocking Block
Exercise
SystemVerilog Object Oriented Programming - Basics
SV OOP - Introduction, Class Data Type & Objects
Video
00:15:05
SV OOP - Constructor, Null Object, Object assignments and copy
Video
00:17:00
SV OOP - Shallow Vs Deep Copy & Summary
Video
00:17:30
Knowledge Check: Basic OOP
Exercise
SystemVerilog Object Oriented Programming - Advanced
SV OOP - Introduction, Inheritance & Super
Video
00:20:50
SV OOP - Static properties & methods and Pass by ref
Video
00:15:23
SV OOP - Polymorphism, cast, Virtual & Parametrised classes, Summary
Video
00:21:53
Knowledge Check: Advanced OOP
Exercise
SystemVerilog Randomization
SV Randomization - Introduction, rand and randc
Video
00:10:58
SV Randomization - Randomize, Pre and Post randomize & Constraints
Video
00:12:52
SV Randomization - Set Membership, Constraints & Summary
Video
00:13:22
Knowledge Check: Randomization
Exercise
SystemVerilog Threads
SV Threads, Events, Mailbox and Semaphores
Video
00:23:11
Knowledge Check : Threads , Events, Semaphore & Mailbox
Exercise
SystemVerilog Virtual Interface
SV Virtual Interface - Introduction, Implementation & Examples
Video
00:17:21
Knowledge Check : Virtual Interface
Exercise
SystemVerilog Functional Coverage
SV Functional Coverage - Introduction & CRCDV
Video
00:15:51
SV Functional Coverage - Covergroup, Coverpoint, Bins, Cross, Methods & Summary
Video
00:17:30
Knowledge Check : Functional Coverage
Exercise
SystemVerilog Labs
SV Labs User Guide
PDF
Lab 1 Solution : Data Types
Video
00:17:56
Lab 2 Solution : Interfaces
Video
00:09:26
Lab 3 Solution : OOP Basics
Video
00:08:51
Lab 4 Solution : Advanced OOP
Video
00:18:09
Lab 5 Solution : Randomization
Video
00:05:41
Lab 6 Solution : Threads, Mailbox & Semaphores
Video
00:22:02
Lab 7 Solution : Transaction
Video
00:09:43
Lab 8 Solution : Transactors
Video
00:09:01
Lab 9 Solution : Scoreboard & Reference Model
Video
00:10:59
Lab 10 Solution : Environment & Testcases
Video
00:11:20
SystemVerilog Lab Manual - for Synopsys VCS
PDF
SV Assignments
Assignment 1
PDF
Solution to Assignment 1
Video
00:15:09
Assignment 2
PDF
Solution to Assignment 2
Video
00:24:45
Assignment 3
PDF
Solution to Assignment 3
Video
00:27:41
Assignment 4
PDF
Solution to Assignment 4
Video
00:29:54
Assignment 5
PDF
Solution to Assignment 5
Video
00:09:05
Questasim - Tool Demos
Questasim- GUI and Batch Mode Usage
Video
00:23:10
Questasim - Coverage Report Generation
Video
00:10:11
Synopsys VCS and Verdi - Tool Demos
VCS- Tool Demo
Video
00:10:14
Verdi Tool Demo - Part-1
Video
00:09:16
Verdi Tool Demo - Part-2
Video
00:07:48
Case Study 1 : Dual Port RAM - SystemVerilog TB
Verification Plan
Video
00:10:18
Testbench Architecture and Verification Flow
Video
00:08:12
Transaction and Generator
Video
00:10:55
Interface and Drivers
Video
00:13:10
Monitors
Video
00:08:56
Scoreboard and Reference Model
Video
00:12:59
Environment and Testcases
Video
00:13:16
Case Study 2 : Maven SoC - SystemVerilog TB
Maven SoC SystemVerilog Verification Environment
Video
00:10:45
SV Mini Project
SV Mini Project (Verification of Counter RTL using SV)
PDF
Counter - TB Architecture and TB Components
Video
00:18:06
Feedback Form - SV,SVA Theory & Labs
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
SV - Module Test
Module Test : SV & SVA
Exercise
Business Communication
6 Exercises • 17 Learning Materials
Channels of Communication
Channels of Communication
Video
00:50:35
Channels of Communication
Exercise
Why and What of Interview
Lecture 1 - All about mindset
Video
00:13:56
Lecture 2 - How to ace a job interview?
Video
00:18:02
Telephone and Video Etiquette Tips for Online Interviews
Telephone and Video Etiquette
Video
00:27:15
Telephone and Video Etiquette
Exercise
Group Discussion
How to ace a Group discussion?
Video
00:19:43
Impression Management
Impression Management at Work Place
Video
00:31:57
Impression Management
Exercise
Resume Writing and Cover Letter
Resume Writing and Cover Letter
Video
00:50:11
Technical content to be included in Resume for RN batches
PDF
Technical content to be included for PD batches
PDF
Upload your Resume for review
Assignment
Professionalism
Professionalism, Gender and Culture Sensitivity
Video
00:25:35
Team Work
Video
00:08:11
Feedback Form
Feedback Form
External Link
Create a winning LinkedIn Profile
How to create a winning LinkedIn profile?
Video
00:37:57
Workplace Awareness
Getting Job Ready
Video
00:34:55
Email Etiquette
Email Writing - Tips and Tricks
Video
00:36:17
Email Etiquette
Exercise
Interpersonal Skills
Key behavioral skills for your workplace
Video
00:34:27
Interpersonal Skills
Exercise
Unsaid Rules of the workplace
Unsaid rules of the workplace
Video
00:38:53
VLSI - Verification - Design Automation Perl
2 Exercises • 10 Learning Materials
PERL Scripting
PERL Scripting - Lecture 1
Video
00:48:16
Knowledge check:Perl1
Exercise
PERL Scripting - Lecture 2
Video
00:41:35
Knowledge check: Perl2
Exercise
PERL Reference Book
PERL Reference Book
PDF
PERL Labs
Perl Labs User Guide
PDF
PERL Lab Manual
PDF
Lab 01 Solution
Video
00:01:34
Lab 02 Solution
Video
00:01:19
Lab 03 Solution
Video
00:01:59
Lab 04 Solution
Video
00:02:15
Lab 05 Solution
Video
00:02:47
VLSI - Verification -Assertion Based Verification-SVA
6 Exercises • 21 Learning Materials
SVA Reference Book
SVA Reference Book
PDF
SVA Introduction & Types of Assertions
What are Assertions?
Video
00:13:07
Necessity of using SystemVerilog Assertions
Video
00:14:46
Types of Assertions
Video
00:14:55
SVA - Knowledge Check - 1
Exercise
SVA Building Blocks, System Functions
SVA Building Blocks
Video
00:17:34
System Functions
Video
00:11:48
SVA - Knowledge Check - 2
Exercise
Writing Sequences and Implication Operators
How to write sequences?
Video
00:11:21
Exercise based on Implication Operators and Timing Windows
Video
00:14:18
Implication Operators
Video
00:24:34
SVA - Knowledge Check - 3
Exercise
Repetition Operators and Sequence Composition
Repetition Operators
Video
00:21:46
Sequence Composition
Video
00:19:46
Methods for Sequences
Video
00:07:21
SVA - Knowledge Check - 4
Exercise
Miscellaneous Concepts and Connecting Assertions to DUT
Miscllenious Cocenpts in SVA
Video
00:07:27
Connecting Assertions to DUT
Video
00:07:59
SVA - Knowledge Check - 5
Exercise
Knowledge Check : SVA
Knowledge Checks : SVA
Exercise
SVA Labs
SVA_Labs_User_Guide
PDF
SVA Lab Solution
Video
00:12:05
SVA Lab Manual - Synopsys VCS
PDF
SVA Case Study
Explanation to Project Specification
Video
00:38:05
Alarm Clock Project Specification
PDF
SVA Assignments
SVA Assignment
PDF
Solution to SVA Assignment
Video
00:26:09
VLSI - Verification -Universal Verification Methodology
13 Exercises • 55 Learning Materials
Universal Verification Methodology Overview
UVM_Introduction
Video
00:43:18
Advanced_UVM_CaseStudies
Video
00:48:13
Knowledge Check : Introduction to UVM
Exercise
UVM Reference Book
UVM - Quick Reference Guide
PDF
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
Video
00:13:48
UVM Base Class Hierarchy
Video
00:14:31
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
Exercise
UVM Factory
UVM Factory - Importance of using factory
Video
00:11:19
UVM Factory - Registration Process
Video
00:06:02
UVM Factory - Create Method and Factory Overriding
Video
00:11:47
Knowledge Check - UVM Factory
Exercise
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
Video
00:10:22
UVM Stimulus Modelling - Overriding the predefined do_ methods
Video
00:10:41
UVM - TB Overview
Video
00:10:44
Knowledge Check - UVM Stimulus Modelling & TB Overview
Exercise
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
Video
00:16:27
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
Video
00:13:13
UVM Reporting Mechanism
Video
00:15:01
Knowledge Check - UVM Phases & Reporting Mechanism
Exercise
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
Video
00:11:35
UVM TLM Ports - TLM FIFO and Analysis Ports
Video
00:13:01
UVM Configuration - Introduction to Configuration Facility
Video
00:13:02
UVM Configuration - Configuration class and Configuration of Virtual Interface
Video
00:09:31
Knowledge Check - UVM TLM Ports and Configuration
Exercise
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Video
00:15:01
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Video
00:16:30
Knowledge Check - UVM - Creating UVM Testbench Components
Exercise
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
Video
00:11:35
UVM Sequences - Starting the sequences and Default Sequence
Video
00:15:17
Knowledge Check - UVM Sequences
Exercise
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
Video
00:13:33
UVM Virtual Sequences & Virtual Sequencers - implementation
Video
00:08:22
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
Exercise
UVM Callbacks & Events
UVM Callbacks
Video
00:09:23
UVM Events
Video
00:09:06
Knowledge Check - UVM Callbacks & Events
Exercise
UVM - Creating Scoreboard
UVM Creating Scoreboard
Video
00:09:20
Knowledge Check - UVM - Creating Scoreboard
Exercise
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
Video
00:15:55
UVM RAL - Adapter, Predictor and Integration
Video
00:20:36
UVM RAL - Definition of Register Sequences
Video
00:11:55
Knowledge Check - UVM RAL
Exercise
UVM - CaseStudies
Advanced_UVM_CaseStudies
Video
00:48:13
UVM Labs
UVM Labs User Guide
PDF
Lab1 Solution : Stimulus Modeling
Video
00:16:02
Lab2 Solution : Factory Overriding
Video
00:08:19
Lab3 Solution : UVM Phases
Video
00:10:22
Lab4 Solution : Creating UVM agent
Video
00:11:44
Lab5 Solution : UVM Sequences
Video
00:13:22
Lab6 Solution : Virtual Interface
Video
00:05:50
Lab7 Solution : Agent Integration
Video
00:08:12
Lab8 Solution : UVM Socreboard
Video
00:06:39
Lab9 Solution : SoC - UVM VE implementation
Video
00:08:41
Lab10 Solution : Coverage & Regression
Video
00:04:33
UVM Lab Manual - Synopsys VCS
PDF
UVM Assignments
UVM Assignment 1
PDF
UVM Assignment 2
PDF
UVM Assignment 3
PDF
Solution to UVM Assignment 3
Video
00:15:39
Solution to UVM Assignment 1
Video
00:14:34
Solution to UVM Assignment 2
Video
00:15:01
Feedback Form - UVM Theory & Labs
Feedback form - Trainer
feedback_form
Feedback form - Mentor
feedback_form
Feedback form - Infrastucture
feedback_form
UVM - Module Test
Module Test : UVM
Exercise
UVM Pilot Project (Router Verification)
Introduction
Video
00:07:06
Project : UVM TB Architecture
Video
00:15:54
Feedback Form - Router Verification Project
External Link
Router Design
10 Learning Materials
Router 1x3 RTL Design
Router_1x3_design - Specification
PDF
Introduction to Router
Video
00:10:53
Router Top Packet Structure
Video
00:07:16
Input Output Protocol
Video
00:04:40
Router Architecture
Video
00:19:17
Router Design Solution Videos
Router_fifo
Video
00:20:58
Router_synchronizer
Video
00:14:06
Router_fsm
Video
00:17:17
Router_register
Video
00:20:58
Router_top
Video
00:19:04
Router Verification Project
4 Learning Materials
Router Specification and TB architecture
Introduction
Video
00:07:06
Project : UVM TB Architecture
Video
00:15:54
Router TB Implementation
TB Implementation : TB Components - Build & Connect Phases
Video
00:23:50
TB Implementation : TB Components - Run Phases and Testcases for Regression
Video
00:26:11
RISC-V Project - DV
7 Learning Materials
RISC-V RV32I Quick reference Guides
RISC-V RV32I reference Card for V-Plan
PDF
RISC-V RV32I - Quick Reference Guide for Instrcutions
PDF
RISC-V Specification
The RISC-V Instruction Set Manual
PDF
MSRV32I Core Design Specification
PDF
RISC-V Processor Verification
RISC-V Verification Plan-1
Video
00:02:10
RISC-V Verification Plan -2
Video
00:02:21
RISC-V TB Architecture
Video
00:11:02
Questasim - Tool Demos
2 Learning Materials
Questasim - Tool Demos
Questasim- GUI and Batch Mode Usage
Video
00:23:10
Questasim - Coverage Report Generation
Video
00:10:11
Course Instructor
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FAQs
1. What is VLSI design and verification?
VLSI design and verification involves creating integrated circuit designs and ensuring their functionality through rigorous testing and simulation processes.
2. What does an advanced VLSI design and verification course include?
Such courses typically cover topics like advanced design methodologies, verification techniques, SystemVerilog, UVM, and DFT concepts.
3. Who should enroll in a VLSI verification course?
Students, engineers, and professionals seeking expertise in design validation and verification techniques for VLSI systems should consider enrolling.
4. What can you expect to learn in a VLSI design and verification course?
Expect to learn digital design basics, verification methods, ASIC flow, and tools like Cadence and Mentor Graphics.
5. How does a VLSI design verification course benefit your career?
It equips you with industry-relevant skills, preparing you for roles in design and verification domains in the semiconductor industry.
6. Why is design verification crucial in VLSI?
It ensures that designs function as intended, reducing costly errors and failures in chip production.
7. What does VLSI design verification and testing involve?
It includes functional verification, formal verification, and manufacturing tests to validate the design's correctness and reliability.
8. What is the focus of advanced VLSI verification?
Advanced VLSI verification focuses on methodologies like UVM, assertion-based verification, and high-level abstraction techniques.
9. What are some key VLSI verification techniques?
Simulation-based verification, formal verification, and emulation are commonly used techniques in VLSI.
10. How are VLSI design and test verification related?
Test verification ensures the design's manufacturability and performance through test pattern generation and fault simulation.
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