OFFER
Design For Testability is one of the essential processes in VLSI Design Flow. It is intended to detect the manufacturing defects in a fabricated chip since the fabrication process's yield is never 100%. DFT methodology offers various techniques to increase the efficiency of the silicon testing process of a fabricated chip. This DFT Training course will cover the necessary basics of silicon testing, the importance of testing, and different DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST.
Also, this course will give the learners a hands-on experience of the implementation of all DFT techniques using the industry-standard tool Tessent from Mentor Graphics.
Any Electronics Engineer with a good knowledge of Digital Electronics, RTL Design using Verilog HDL, and moderate programming skills can learn DFT concepts from this course and grow as a DFT Engineer.
Pre-requisites: Any electronics/electrical engineering graduate with a good knowledge of Digital Electronics and RTL programming using Verilog HDL
1: DFT Theory
2: DFT Reference Book
14 January 2021
its a wonderful course
13 January 2021
good
24 December 2020
content is very helpful in understanding DFT for a beginner
21 December 2020
This course helped a lot in Understanding the Basics of DFT.
11 December 2020
Very good explanations of concepts and lab sessions.
30 November 2020
good fundamentals with tool skills
28 November 2020
The content of the course was useful and explained precisely
12 October 2020
good fundamentals & explanation of concepts
