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Design for Testability

  • 5.0 | 1 Rating
  • 21 Students enrolled
  • Certified course

About Course

  Language English

Design For Testability is one of the essential processes in VLSI Design Flow. It is intended to detect the manufacturing defects in a fabricated chip since the fabrication process's yield is never 100%. DFT methodology offers various techniques to increase the efficiency of the silicon testing process of a fabricated chip. This DFT Training course will cover the necessary basics of silicon testing, the importance of testing, and different DFT techniques such as SCAN Insertion, ATPG, JTAG, and BIST.

Also, this course will give the learners a hands-on experience of the implementation of all DFT techniques using the industry-standard tool Tessent from Mentor Graphics.

Any Electronics Engineer with a good knowledge of Digital Electronics, RTL Design using Verilog HDL, and moderate programming skills can learn DFT concepts from this course and grow as a DFT Engineer.

Pre-requisites: Any electronics/electrical engineering graduate with a good knowledge of Digital Electronics and RTL programming using Verilog HDL

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Curriculum

  • 1: DFT Theory

  • Lecture 1 Introduction to DFT 11:15
  • Lecture 2 Types of Testing 08:24
  • Lecture 3 Basic Testing Principles 11:38
  • Lecture 4 Fault Collapsing 12:27
  • Lecture 5 What is DFT? 10:50
  • Lecture 6 DFT Techniques - Ad-hoc Techniques 10:15
  • Lecture 7 DFT Techniques- Structured Techniques 09:15
  • Lecture 8 BIST & boundary Scan 12:07
  • Quiz 1 DFT Theory - Quiz 15 Questions
  • 2: DFT Reference Book

  • Lecture 9 DFT Reference Book 139 Pages
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