Design for Testability
Optimize digital design for testability with Maven Silicon. Explore strategies and techniques for robust testing processes in VLSI and hardware development.
₹9900.00 ₹19900.00 50% OFF
/CourseBundles(50)/632-Design_for_Testability-min.png)
Course Overview
Welcome to the Design for Testability course – your comprehensive exploration of testing methodologies in the realm of electronic design. From Intro to Testing to hands-on DFT Labs, this course delves into key modules covering fault collapsing, ATPG, DFT basics, scan insertion, test compression, boundary scan, BIST, and more. Engage in practical labs to reinforce your knowledge and be well-prepared to implement robust testable designs. Join us on this enlightening journey into the world of Design for Testability!
Course Curriculum
1 Subject
Design for Testability - DFT
6 Exercises • 51 Learning Materials
Reference Books
DFT Theory - Reference Book
Tessent Shell
Intro to Testing
Introduction to Testing and DFT
Verification vs Testing
Faults and Types of Testing
Levels of Testing
Fault Modelling
Knowledge check: Introduction to testing
Fault Collapsing
Fault Collapsing Part-1
Fault Collapsing Part-2
Fault Collapsing Part-3
Introduction to ATPG
Introduction to ATPG
Combinational ATPG
D-Algorithm
Fault Classes and Fault Simulation
Fault Classes
Additional Fault Models part-1
Additional Fault Models part-2
Fault Simulation
Knowledge check: Fault modelling
DFT - Basics
What is DFT?
Classification of DFT Techniques
Structured DFT Techniques
Knowledge check: DFT techniques
Scan Insertion & Test Compression
Scan Insertion Part - 1
Scan Insertion Part - 2
Scan Insertion Part - 3
Scan Insertion Part - 4
Hierachical DFT Flow
Test Compression
Knowledge check: DFT techniques
Boundary Scan & BIST
Boundary Scan
JTAG vs IJTAG
Introduction to BIST, LBIST & MBIST
Knowledge check: DFT techniques
Miscellaneous Concepts
Design Rule Checks
How to improve Test Coverage
Fault Diagnosis
Tessent Shell Overview
Intro to Tessent
System Modes
TSDB Overview
Knowledge check: Tessent shell
DFT - Labs
DFT - Lab Manual
Solution to Lab 01
Solution to Lab 02
Solution to Lab 03
Solution to Lab 04
Solution to Lab 05
Solution to Lab 06
Solution to Lab 07
Solution to Lab 08
Solution to Lab 09
Solution to Lab 10
Solution to Lab 11
Solution to Lab 12
Solution to Lab 13
Solution to Lab 14
Solution to Lab 15
Course Instructor
/101894-Maven_Logo_(elearn_profile_pic)_(2).png){kind=logo}
Sivakumar P R
17 Courses • 1950 Students
CEO and Founder, Maven Silicon
Ratings & Reviews
4.7 /5
296 ratings
●
280 reviews
5
4
3
2
1
Get in touch
We'd love to hear from you!
Visit us
Come say hello at our office.
# 21/1A, III Floor, MS Plaza, Gottigere,
Bannerghatta Road, Bangalore - 560076
Call us
Mon - Sat from 8am to 7pm
080 6909 6300
Online VLSI Courses
Digital Design - Hands On
VLSI Design Methodologies
VLSI System On Chip Design - Overview
Blended VLSI Programs
Blended VLSI Physical Design
Corporate
By clicking on Continue, I accept the Terms & Conditions,
Privacy Policy & Refund Policy