RISC-V ISA & RV32I RTL Architecture Design
This RISC-V training course trains you extensively on the RTL design using Digital Electronics which includes the concepts of combinational, sequential, FSM logic designs and Memories. It is composed of modules that explain the concepts of Logic Gates, Adder, Subtractor, Decoder, Encoder, Multiplexer, Demultiplexer, Flipflops, Latches, Counters, Registers, Memories and Finite state machine.
Also, the STA module explains the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that one can implement to improve the speed of the logic circuits.
Finally, this course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to improve the processor performance, exploring various pipeline architectures.
1: VLSI Introduction
2: SoC Design
3: ASIC Vs FPGA
4: VLSI Design Flow
5: Knowledge Check
6: Digital Electronics
7: Number Systems and Codes