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RISC-V ISA & RV32I RTL Architecture Design

5
(1 rating)
Course Instructor Sivakumar P R
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Course Overview

Course Curriculum

1 Subject

RISC-V ISA &amp RV32I RTL Architecture Design

1 Exercises 48 Learning Materials

VLSI Introduction

Why VLSI ?

Video
5:30

SoC Design

Smart Phone SoC

Video
5:25

System On Chip Design Architecture and Methodology

Video
10:15

ASIC Vs FPGA

ASIC Vs FPGA

Video
6:33

VLSI Design Flow

VLSI Front-End Design Flow Part I

Video
5:50

VLSI Front-End Design Flow Part II

Video
19:6

VLSI Back-End Design Flow

Video
10:40

Knowledge Check : Introduction to VLSI

Exercise

Digital Electronics

Introduction to Digital Electronics

Video
13:26

Number Systems and Codes

Number Systems and Codes

Video
37:45

Logic Circuits

Logic Circuits

Video
55:7

Combinational Circuits

Combinational Circuits - I

Video
28:25

Combinational Circuits - II

Video
44:8

Sequential Circuits

Sequential Circuits - I

Video
40:58

Sequential Circuits - II

Video
45:15

Finite State Machines

FSM

Video
37:39

Memories

Memories

Video
25:54

STA : Introduction

Why & What is Timing Analysis?

Video
7:40

Types of Timing Analysis

Video
10:22

False Paths & Multi Cycle Paths

Video
19:36

STA in Design Flow

Video
5:24

STA: Clock

Clock - Part -1

Video
17:35

Clock - Part - 2

Video
17:41

STA : Timing Parameters

Timing Parameters in STA - Part-1

Video
15:49

Timing Parameters in STA - Part-2

Video
13:58

Timing Parameters in STA - Part-3

Video
10:24

STA: Timing Analysis Procedure

Timing Analysis on Sequential Circuits - Part-1

Video
18:30

Timing Analysis on Sequential Circuits - Part-2

Video
12:48

STA Procedure

Video
10:27

STA : Techniques to Improve Timing

Different Techniques to improve timing

Video
12:51

RISC-V Instruction Set Architecture

Why RISC-V Processor?

Video
6:50

RISC-V processor overview

Video
10:24

RISC-V ISA Overview

Video
12:13

RV32I R Type Instruction

Video
9:29

RV32I I Type Instruction

Video
7:47

RV32I S and B Type Instructions

Video
11:55

RV32I J and U Type Instructions

Video
12:35

RV32I Assembly Programs and Summary

Video
19:22

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

Course Instructor

tutor image

Sivakumar P R

17 Courses   •   1935 Students

CEO and Founder, Maven Silicon

Ratings & Reviews

5 /5

2 ratings

1 reviews

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1

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S
Susmitha

5 months ago

NG
Nickolay Gilimovich

2 years ago

good

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