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VLSI SoC Design Course

RISC-V ISA & RV32I RTL Architecture Design

  • 5.0 | 1 Rating
  • 3 Students enrolled
  • Certified course

About Course

  Language English

RISC-V ISA & RV32I RTL Architecture Design

This RISC-V training course trains you extensively on the RTL design using Digital Electronics which includes the concepts of combinational, sequential, FSM logic designs and Memories. It is composed of modules that explain the concepts of Logic Gates, Adder, Subtractor, Decoder, Encoder, Multiplexer, Demultiplexer, Flipflops, Latches, Counters, Registers, Memories and Finite state machine.

Also, the STA module explains the importance of timing analysis, how to do the timing analysis on both combinational Logic Circuits and Sequential Circuits and the different strategies that one can implement to improve the speed of the logic circuits.

Finally, this course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to improve the processor performance, exploring various pipeline architectures.

Modules:

  1. VLSI SoC Design
  2. Design Electronics
  3. Static Timing Analysis
  4. RISC-V Instruction Set Architecture
  5. RISC-V RTL Design
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Curriculum

  • 1: VLSI Introduction

  • Lecture 1 Why VLSI ? 05:30
  • 2: SoC Design

  • Lecture 2 Smart Phone SoC 05:24
  • Lecture 3 System On Chip Design Architecture and Methodology 10:15
  • 3: ASIC Vs FPGA

  • Lecture 4 ASIC Vs FPGA 06:33
  • 4: VLSI Design Flow

  • Lecture 5 VLSI Front-End Design Flow Part I 05:49
  • Lecture 6 VLSI Front-End Design Flow Part II 19:06
  • Lecture 7 VLSI Back-End Design Flow 10:40
  • 5: Knowledge Check

  • Quiz 1 Knowledge Check - VLSI SoC Design 5 Questions
  • 6: Digital Electronics

  • Lecture 8 Introduction to Digital Electronics 13:25
  • 7: Number Systems and Codes

  • Lecture 9 Number Systems and Codes 37:44
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